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Volumn 49, Issue 4, 2000, Pages 348-359

Generic universal switch blocks

Author keywords

Analysis; Architecture; Design; Digital; Gate array; Programmable logic array

Indexed keywords


EID: 0000301419     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.844347     Document Type: Article
Times cited : (32)

References (15)
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    • Dec.
    • R.I. Greenberg, "The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay," IEEE Trans. Computers, vol. 43, no. 12, pp. 1,358-1,364, Dec. 1994.
    • (1994) IEEE Trans. Computers , vol.43 , Issue.12
    • Greenberg, R.I.1
  • 6
    • 0022141776 scopus 로고
    • Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing
    • Oct.
    • C.H. Leiserson, "Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing," IEEE Trans. Computers, vol. 34, no. 10, pp. 892-901, Oct. 1985.
    • (1985) IEEE Trans. Computers , vol.34 , Issue.10 , pp. 892-901
    • Leiserson, C.H.1
  • 7
    • 0001528317 scopus 로고
    • Top-Down Hierarchical Global Routing for Channelless Gate Arrays Based on Linear Assignment
    • U. Lauther, "Top-Down Hierarchical Global Routing for Channelless Gate Arrays Based on Linear Assignment," Proc. IFIP VLSI 87, pp. 109-120, 1987.
    • (1987) Proc. IFIP VLSI , vol.87 , pp. 109-120
    • Lauther, U.1
  • 8
    • 0031169872 scopus 로고    scopus 로고
    • Hierarchical Interconnection Structures for Field Programmable Gate Arrays
    • Y.T. Lai and P.T. Wang, "Hierarchical Interconnection Structures for Field Programmable Gate Arrays," IEEE Trans. VLSI Systems, pp. 186-196, 1997.
    • (1997) IEEE Trans. VLSI Systems , pp. 186-196
    • Lai, Y.T.1    Wang, P.T.2
  • 10
    • 0026124456 scopus 로고
    • Flexibility of Interconnection Structures for Field-Programmable Gate Arrays
    • J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," IEEE J. Solid State Circuits, vol. 26, no. 3, pp. 277-282, 1991.
    • (1991) IEEE J. Solid State Circuits , vol.26 , Issue.3 , pp. 277-282
    • Rose, J.1    Brown, S.2
  • 11
    • 33747426140 scopus 로고
    • Improving FPGA Routing Architectures Using Architecture and CAD Interactions
    • B. Tseng, J. Rose, and S. Brown, "Improving FPGA Routing Architectures Using Architecture and CAD Interactions," Proc. IEEE Conf. Computer Design, pp. 99-104, 1992.
    • (1992) Proc. IEEE Conf. Computer Design , pp. 99-104
    • Tseng, B.1    Rose, J.2    Brown, S.3
  • 12
    • 0028697847 scopus 로고
    • Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
    • N. Togawa, M. Sato, and T. Ohtsuki, "Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 156-163, 1994.
    • (1994) Proc. IEEE/ACM Int'l Conf. Computer-Aided Design , pp. 156-163
    • Togawa, N.1    Sato, M.2    Ohtsuki, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.