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Volumn 49, Issue 2, 2006, Pages 158-172

Minimal regular 2-graphs and applications

Author keywords

2 graph; Graph; Regular factor; Switch box design

Indexed keywords


EID: 33344459940     PISSN: 10069283     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11425-004-5192-y     Document Type: Article
Times cited : (2)

References (13)
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  • 9
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    • General models and a reduction design technique for FPGA switch box designs
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    • A comment on "general universal switch blocks"
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.