Energy-aware clock-frequency assignment in microprocessors and memory devices for dynamic voltage scaling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 6, 2007, Pages 1030-1040

  Cho, Youngjin ^a,b   Chang, Naehyuck ^a,b  

^a Seoul National University ^*

^b Seoul National University   (South Korea)

Author keywords

Energy management; Power management; Real time systems

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS; SCALING LAWS;

CLOCK FREQUENCY; DYNAMIC VOLTAGE SCALING; POWER MANAGEMENT;

DATA STORAGE EQUIPMENT;

EID: 34247574868     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.885835     Document Type: Article

References (22)

1. Y. Cho and N. Chang, "Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling," in Proc. Int. Symp. Low Power Electron. Des., 2004, pp. 387-392.
2. F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," in Proc. 36th Symp. Foundations Comput. Sci., 1995, pp. 374-382.
3. T. Ishihara and H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," in Proc. Int. Symp. Low Power Electron. and Des., 1998, pp. 197-202.
4. H. Shim, Y. Cho, and N. Chang, "Power saving in hand-held multimedia systems using MPEG-21 digital item adaptation," in Proc. IEEE Workshop ESTIMedia, 2004, pp. 13-18.
5. T. L. Martin and D. P. Siewiorek, "Nonideal battery and main memory effects on CPU speed-setting for low power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 29-34, Feb. 2001.
6. B. Egger, J. Lee, and H. S. Shin. (2004). "An application-specific and adaptive power management technique," in Proc, 1st Int. Workshop Power-Aware Real-Time Comput. [Online]. Available: http://www.cs.pitt. edu.PARC/
7. F. Zhang and S. T. Chanson, "Processor voltage scheduling for real-time tasks with non-preemptible sections," in Proc. Real-Time Syst. Symp., 2002, pp. 235-245.
8. T. Simunic, L. Benini, A. Acquaviva, P. Glynn, and G. D. Micheli, "Dynamic voltage scaling and power management for portable systems," in Proc. 38th Des. Autom. Conf., 2001, pp. 524-529.
9. X. Fan, C. S. Ellis, and A. R. Lebeck, "The synergy between power-aware memory systems and processor voltage," in Proc. Power-Aware Comput. Syst., 2003, pp. 164-179.
10. R. Jejurikar and R. Gupta, "Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems," in Proc. Int. Symp. Low Power Electron. and Des., 2004, pp. 78-81.
11. J. Zhuo and C. Chakrabarti, "System-level energy-efficient dynamic task scheduling," in Proc. 42nd Des. Autom. Conf., 2005, pp. 628-631.
12. Y. Choi, N. Chang, and T. Kim, "DC-DC converter-aware power management for battery-operated embedded systems," in Proc. 42nd Des. Autom. Conf., 2005, pp. 895-900.
13. H. Shim, Y. Joo, Y. Choi, H. G. Lee, and N. Chang, "Low-energy off-chip SDRAM memory systems for embedded applications," Trans. Embedded Comput. Syst., vol. 2, no. 1, pp. 98-130, Feb. 2003.
14. R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in Proc. 41st Des. Autom. Conf., 2004, pp. 275-280.
15. L. Niu and G. Quan, "Reducing both dynamic and leakage energy consumption for hard real-time systems," in Proc. Int. Conf Compilers, Architecture, and Synthesis Embedded Syst., 2004, pp. 140-148.
16. J. L. Wong, G. Qu, and M. Potkonjak, "Power minimization in QoS sensitive systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 6, pp. 553-561, Jun. 2004.
17. S. Boyd and L. Vandenberghe, Convex Optimization. Cambridge, U.K.: Cambridge Univ. Press, 2004.
18. M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. Hoboken, NJ : Wiley, 1997.
19. F. Xie, M. Martonosi, and S. Malik, "Compile-time dynamic voltage scaling settings: Opportunities and limits," in Proc. ACM SIGPLAN Conf. Program. Language Des. and Implementation, 2003, pp. 49-62.
20. T. Wang, "Global optimization for constrained nonlinear programming," Ph.D. dissertation, Dept. Comput. Sci., Univ. Illinois, Urbana, IL, Dec. 2000.
21. Micron Technology Inc., Datasheet of Micron Synchronous SDRAM (MT48LC16M8A2), 2003.
22. Y. Joo, Y. Choi, H. Shim, H. G. Lee, K. Kim, and N. Chang, "Energy exploration and reduction of SDRAM memory systems," in Proc. 39th Des. Autom. Conf., 2002, pp. 892-897.