Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 78-81

  Jejurikar, Ravindra ^a   Gupta, Rajesh ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Critical speed; DVS; EDF scheduling; Low power; Procrastication; Real time systems; Resource standby energy

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; FLASH MEMORY; REAL TIME SYSTEMS; SCHEDULING;

CRITICAL SPEED; DYNAMIC VOLTAGE SCALING (DVC); EDF SCHEDULING; LOW POWER; PROCRASTICATION; RESOURCE STANDBY ENERGY;

EMBEDDED SYSTEMS;

EID: 16244399186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013261     Document Type: Conference Paper

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