Dynamic cluster resizing

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 375-377

  González, José ^a   González, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTATIONAL METHODS; COMPUTER HARDWARE; ESTIMATION; MICROPROCESSOR CHIPS; QUEUEING THEORY;

COPY QUEUE; FLOATING POINT QUEUE; INTEGER QUEUE; MEMORY QUEUE; TURN-OFF RESOURCE;

COMPUTER ARCHITECTURE;

EID: 0344982083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. V. Agarwal, M.S. Hrishikesh, S.W. Keckler and D. Burger. "Clock Rate versus IPC: The End of the Road for Conventional Architectures", in Proc. of the Int. Symp. on Computer Architecture, 2000.
2. D. Albonesi. "Dynamic IPC/Clock Rate Optimization. Proc. of the Int. Symp. on Computer Architecture. pp. 282-292, 1998.
3. A. Baniasadi, A. Moshovos. "Asymmetric-Frequency Clustering: A Power Aware Back-End for High-Performance Processors". Proc. Int. Symp. on Low Power Electronics Design, 2002.
4. A. Bayuktosunoglu, S.Shuster, D. Brooks, P. Bose, P. Cook and D. Albonesi. "An Adaptive Issue Queue for Reduced Power at High Performance". Workshop on Power-Aware Computer Systems, 2000.
5. R. Canal, J.M. Parcerisa and A. Gonzalez. "A Cost-Effective Clustered Architecture". In Proc. of the Int. Conf. on Parallel Architectures and Compilation Techniques, 1999.
6. S. Palacharla. "Complexity-Effective Superscalar Processors". PH.D. Thesis, Univ. of Wisconsin-Madison, 1998.
7. D. Ponomarev, G. Kucuk, K. Ghose. "Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources". Proc of Int. Symp on Microarchitecture, 2000.
8. G. Semeraro, D. H. Albonesi, S.G.Dropsho, G. Magklis, S. Dwarkadas and M.L. Scott. "Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture". Proc. Int. Symp. on Microarchitecture, 2002.
9. J.S. Seng, E. S. Tune, D.M. Tullsen. "Reducing Power with Dynamic Critical Path Information". Proc. International Symp. on Microarchitecture, 2000.