A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 263-266

  Cheng, Kuo Hsing ^a   Yang, Wei Bin ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; LOCKS (FASTENERS); OSCILLISTORS; SPICE; VARIABLE FREQUENCY OSCILLATORS;

DIGITAL PHASE LOCKED LOOPS; HIGH NOISE; HSPICE SIMULATIONS; LOW POWER; OPERATING FREQUENCY; PHASED LOCKED LOOPS; TOTAL POWER CONSUMPTION;

PHASE LOCKED LOOPS;

EID: 84966292320     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031582     Document Type: Conference Paper

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