An integrated memory array processor for embedded image recognition systems

IEEE Transactions on Computers

Volumn 56, Issue 5, 2007, Pages 622-634

  Kyo, Shorin ^a   Okazaki, Shin'ichiro ^a   Arai, Tamio ^b  

^a NEC CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Image processing; Image recognition; Memory array processor; Parallel language; Parallel SIMD processor

Indexed keywords

C (PROGRAMMING LANGUAGE); IMAGE RECOGNITION; MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SYSTOLIC ARRAYS;

EMBEDDED IMAGE RECOGNITION SYSTEMS; INTEGRATED MEMORY ARRAY PROCESSOR; PARALLEL LANGUAGE; VIDEO IMAGE RECOGNITION;

IMAGING SYSTEMS;

EID: 34147161065     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.1010     Document Type: Article

References (42)

1. J.H. Ahn et al., "Evaluating the Imagine Stream Architecture," Proc. 31st Ann. Int'l Symp. Computer Architecture, pp. 14-25, 2004.
2. R.S. Bajwa et al., "Image Processing with the MGAP: A Cost Effective Solution," Proc. Seventh Int'l Parallel Processing Symp., pp. 439-443, 1993.
3. G. Borgefors, "Distance Transformations in Digital Images," Computer Vision, Graphics, and Image Processing, vol. 34, pp. 344-371, 1986.
4. J. Canny, "A Computational Approach to Edge Detection," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 9, no. 6, pp. 679-698, 1986.
5. V. Cantoni and L. Lombardi, "Hierarchical Architectures for Computer Vision," Proc. Euromicro Workshop Parallel and Distributed Processing, pp. 392-398, 1995.
6. R. Cypher and J.L.C. Sanz, "SIMD Architectures and Algorithms for Image Processing and Computer Vision," IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 37, no. 12, pp. 2158-2174, 1989.
7. M.J. Duff, "CLIP 4: A Large Scale Integrated Circuit Array Parallel Processor," Proc. IEEE Int'l Joint Conf. Pattern Recognition, pp. 728-733, Nov. 1976.
8. A.L. Fisher et al., "Architecture of a VLSI SIMD Processing Element," Proc. IEEE Int'l Conf. Computer Design: VLIS Computer Process, pp. 324-327, 1987.
9. R.J. Fisher et al., "The Scc Compiler: SWARing at MMX and 3DNow!," Lecture Notes in Computer Science, vol. 1863, pp. 399-414, 2000.
10. B. Flachs et al., "A Streaming Processing Unit for a CELL Processor," Int'l Solid State Circuits Conf. Digest of Technical Papers, vol. 7.4, pp. 134-135, 2005.
11. T.J. Fountain, K.N. Matthews, and M.J.B. Duff, "The CLIP7A Image Processor," IEEE Trans. Pattern Analysis and Machine Intelligence vol. 10, no. 3, pp. 310-319, 1988.
12. Y. Fujita, N. Yamashita, and S. Okazaki, "IMAP: Integrated Memory Array Processor," J. Circuits, Systems, and Computers, vol. 2, no. 3, pp. 227-245, 1992.
13. J. Geerlings et al., "A Single-Chip MPEG2 CODEC for DVD+RW," Int'l Solid State Circuits Conf. Digest of Technical Papers, vol. 2.2, 2003.
14. D.W. Hammerstrom and D.P. Lulich, "Image Processing Using One-Dimensional Processor Arrays," Proc. IEEE, vol. 84, no. 7, pp. 1005-1018, 1996.
15. J. Hart et al., "Implementation of a 4th-Generation 1.8GHz Dual-Core SPARC V9 Microprocessor," Int'l Solid State Cicrcuits Conf. Digest of Technical Papers, vol. 10.3, pp. 186-187, 2005.
16. D. Helman and J. JaJa, "Efficient Image Processing Algorithms on the Scan Line Array Processor," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 17, no. 1, pp. 47-56, Jan. 1995.
17. W.D. Hills, The Connection Machine. MIT Press, 1985.
18. P.P. Jonker, "Architectures for Multidimensional Low- and Intermediate Level Image Processing," Proc. IAPR Workshop Machine Vision Applications, pp. 307-316, 1990.
19. P.P. Jonker, "Why Linear Arrays Are Better Image Processors," Proc. IAPR Conf. Pattern Recognition, vol. 3, pp. 334-338, 1994.
20. A.H. Kamalizad et al., "Fast Parallel FFT on a Reconfigurable Computation Platform," Proc. 15th Symp. Computer Architecture and High Performance Computing, pp. 254-259, 2003.
21. R.P. Kleihorst et al., "Xetal: A Low-Power High-Performance Smart Camera Processor," Proc. IEEE Int'l Symp. Circuits and Systems, vol. 5, pp. 215-218, 2001.
22. E.R. Komen, "Low-Level Image Processing Architectures," PhD thesis, Delft Univ. of Technology, 1990.
23. C.E. Kozyrakis and D.A. Patterson, "Scalable Vector Processors for Embedded Systems," IEEE Micro, vol. 23, no. 6, pp. 36-45, Nov./Dec. 2003.
24. C.E. Kozyrakis and D.A. Patterson, "Overcoming the Limitation of Conventional Vector Processor," Proc. 30th Ann. Int'l Symp. Computer Architecture, pp. 399-409, 2003.
25. S. Kyo and S. Sato, "Efficient Implementation of Image Processing Algorithms on Linear Processor Arrays Using the Data Parallel Language 1DC," Proc. IAPR Workshop Machine Vision Applications (MVA '96 , pp. 160-165, 1996.
26. S. Kyo et al., "A Parallelizing Method for Implementing Image Processing Tasks on SIMD Linear Processor Arrays," Proc. IEEE Workshop Computer Architecture for Machine Perception, pp. 180-184, 1997.
27. S. Kyo et al., "A Robust Vehicle Detecting and Tracking System for Wet Weather Conditions Using the IMAP-VISION Image Processing Board," Proc. IEEE Int'l Conf. Intelligent Transportation Systems, pp. 423-428, 1999.
28. S. Kyo et al., "A 51.2GOPS Scalable Video Recognition Processor for Intelligent Cruise Control Based on a Linear Array of 128 4-Way VLIW Processing Elements," J. Solid State Circuits, vol. 38, no. 11, pp. 1992-2000, Nov. 2003.
29. S. Kyo et al., "A 51.2GOPS Programmable Video Recognition Processor for Vision based Intelligent Cruise Control Applications," IEICE Trans. Information and Systems, vol. E87-D, no. 1, pp. 136-145, Jan. 2004.
30. S. Kyo et al., "An Extended C Language and a SIMD Compiler for Efficient Implementation of Image Filters on Media Extended Micro-Processors," Proc. Conf. Advanced Concepts for Intelligent Vision Systems (ACIVS), pp. 234-241, 2003.
31. S. Kyo, "Design and Development of a Linear Processor Array (LPA) Architecture for Accelerating Image Recognition Tasks," PhD thesis, Univ. of Tokyo, 2004.
32. S. Kyo et al., "An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA), pp. 132-145, 2005.
33. A. Merigot, B. Zavidovique, and F. Devos, "SPHINX: A Pyramidal Approach to Parallel Image Processing," Proc. IEEE Workshop Computer Architecture and Pattern Analysis Image Database Management, pp. 107-111, 1985.
34. S. Naffziger et al., "The Implementation of a 2-core Multi-Threaded Itanium-Family Processor," Int'l Solid State Circuits Conf. Digest of Technical Papers, vol. 10.1, pp. 182-183, 2005.
35. H. Okano et al., "An 8-way VLIW Embedded Multimedia Processor Built in 7-layer Metal 0.11um CMOS Technology," Int'l Solid State Cicruits Conf. Digest of Technical Papers, pp. 374-375, 2002.
36. T. Poggio et al., "The MIT Vision Machine," Proc. Image Understanding Workshop, pp. 177-198, 1988.
37. J.C. Russ, The Image Processing Handbook. CRC Press, 1994.
38. T. Shiota et al., "A 51.2 GOPS 1.0GB/s-DMA Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors," Int'l Solid State Circuits Conf. Digest of Technical Papers, vol. 10.7, pp. 194-195, 2005.
39. H. Singh et al., "MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications," IEEE Trans. Computers, vol. 49, no. 5, pp. 465-481, May 2000.
40. G.L. Steele Jr., "Languages for Massively Parallel Computers," Proc. Second Symp. Frontiers of Massively Parallel Computation, pp. 3-13, 1988.
41. G.M. Van Waveren, "High Performance Fortran," Lecture Notes in Computer Science, vol. 797, pp. 429-433, 1994.
42. J.A. Webb, "Steps Toward Architecture-Independent Image Processing," Computer, pp. 21-31, 1992.