A 0.5-V 1-msample/s 60-dB SNDR track-and-hold circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 45-46

  Chatterjee, Shouri ^a   Kinget, Peter ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POWER GENERATION; VOLTAGE CONTROL;

VOLTAGE BOOSTING; VOLTAGE DESIGN TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 39749137569     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. The International Technology Roadmap for Semiconductors (2004 edition), ITRS, 2004, Technical Report, http://public.itrs.net.
2. S. Chatterjee, Y. Tsividis and P. Kinget, "0.5-V analog circuit techniques and their application in OTA and filter design," IEEE J. of Solid-State Circuits, vol. 40, no. 12, pp. 2373-2387, Dec. 2005.
3. Q. Huang, "Low voltage and low power aspects of data converter design," in Proc. European Solid State Circuits Conference, Sep. 2000, pp. 11-17.
4. M. Ishikawa and T. Tsukahara, "An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H," IEEE J. of Solid-State Circuits, vol. 24, no. 6, pp. 1485-1491, Dec. 1989.
5. J. Steensgaard, "Bootstrapped low-voltage analog switches," in IEEE International Symposium on Circuits and Systems, vol. 2, May 1999, pp. 29-32.
6. J. Sauerbrey, D. Schmitt-Landsiedel and R. Thewes, "A 0.5-V 1-μW successive approximation ADC," IEEE J. of Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, Jul. 2003.