Low overhead delay testing of ASICS

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 534-542

  Gillis, Pamela ^a   McCauley, Kevin ^b   Woytowich, Francis ^a   Ferko, Andrew ^a  

^a IBM   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTER SOFTWARE; CORRELATION METHODS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MICROPROCESSOR CHIPS; VOLTAGE CONTROL;

ASIC DESIGNS; DELAY TESTING; DESIGN AUTOMATION SOFTWARE; INTEGRATED CIRCUIT (IC) DEFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 18144378835     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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