A Background Calibration Technique for Multibit/Stage Pipelined and Time-Interleaved ADCs

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 6, 2006, Pages 448-452

  El Sankary, Kamal ^a   Sawan, Mohamad ^a,b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b Polystim Labora tory   (Canada)

Author keywords

ADC (TIADC); analog to digital converter (ADC); Background calibration; multibit stage; pipelined ADC; time interleaved

Indexed keywords

BIT ERROR RATE; CALIBRATION; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; NONLINEAR SYSTEMS;

BACKGROUND CALIBRATION; PIPELINED ADC; TIME INTERLEAVED ADC (TIADC);

ANALOG TO DIGITAL CONVERSION;

EID: 33947604423     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.873831     Document Type: Article

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