Resource efficiency of the GigaNetIC chip multiprocessor architecture

Journal of Systems Architecture

Volumn 53, Issue 5-6, 2007, Pages 285-299

  Niemann, Jörg Christian ^a   Puttmann, Christoph ^a   Porrmann, Mario ^a   Rückert, Ulrich ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

ASIC; Chip multiprocessor; FPGA; GigaNetIC; GigaNoC; Network on chip; Rapid prototyping; System on chip

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER OPERATING SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; RAPID PROTOTYPING;

GIGANETIC; GIGANOC; NETWORK ON CHIP; SYSTEM ON CHIP;

COMPUTER ARCHITECTURE;

EID: 33947215026     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2006.10.007     Document Type: Article

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