A scalable parallel SoC architecture for network processors

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Volumn , Issue , 2005, Pages 311-313

  Niemann, Jörg Christian ^a   Porrmann, Mario ^a   Rückert, Ulrich ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE ACCELERATORS; NETWORK PROCESSING; NETWORK PROCESSORS; SYSTEM ON CHIP (SOC);

COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ENERGY UTILIZATION; INTERNET; NETWORK PROTOCOLS; PARALLEL PROCESSING SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 26844492080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2005.13     Document Type: Conference Paper

References (8)

1. J.-C. Niemann et al., A holistic methodology for network processor design, in Proc. of the Workshop on High-Speed Local Networks, pp. 583-592, 2003, Königswinter, Germany.
2. P. Guerrier, A. Greiner, A generic architecture for on-chip packet-switched interconnections, in Proc. of DATE 2000, pp. 250 - 256.
3. A. Jantsch, H. Tenhunen, Networks on Chip, Kluwer Academic Publishers, 2003.
4. W.J, Dally, B. Towles, Route packets, not wires: On-chip inter-connection networks, in Proc. of DAC 2001, pp. 684-689.
5. J. Duato, S. Yalamanchili, L. M. Ni, Interconnection Networks: An Engineering Approach, Morgan Kaufmann, 2003.
6. D. Langen, et al, Implementation of a RISC Processor Core for SoC Designs, in Proc. of the IEEE Workshop on Heterogeneous reconfigurable Systems-on-Chip, 2002.
7. U. Kastens, D. K. Le, A. Slowik, M Thies, Feedback Driven Instruction-Set Extension, in Proc. LCTES'04, Washington. D.C., USA, June 2004.
8. J.-C. Niemann et al., Network Application Driven Instruction Set Extensions for Embedded Processing Clusters, In Proc. PARELEC 2004, pp. 209-214, Dresden, Germany, 2004.