Local-damascene-FinFET DRAM integration with p+ doped poly-silicon gate technology for sub-60nm device generations

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 315-318

  Kim, Yong Sung ^a   Lee, Sang Hyeon ^a   Shin, Soo Ho ^a   Han, Sung Hee ^a   Lee, Ju Yong ^a   Lee, Jin Woo ^a   Han, Jun ^a   Yang, Seung Chul ^a   Sung, Joon Ho ^a   Lee, Eun Cheol ^a   Song, Bo Young ^a   Lee, Dong Jun ^a   Bae, Dong Il ^a   Yang, Won Suk ^a   Park, Yang Keun ^a   Lee, Kyu Hyun ^a   Roh, Byung Hyuk ^a   Chung, Tae Young ^a   Kim, Kinam ^a   Lee, Wonshik ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS;

DAMASCENE GATE STRUCTURE; THIN BODY TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33847755493     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Y. Kim et al., "The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm feature size and beyond," VLSI Technical Digest, pp.11-12, 2003.
2. J. Y. Kim et al., "S-RCAT (Sphere-shaped-Recess-Channel- Array-Transistor) Technology for 70nm DRAM feature size and beyond," VLSI Technical Digest, pp.34-35, 2005.
3. R. Katsumata et al., "Fin-Array-FET on bulk silicon for sub-100nm