Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2005, Pages 161-168

  Dimitroulakos, Gregory ^a   Galanis, Michails D ^a   Goutis, Costas E ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CODES (STANDARDS); DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS;

DATA REUSE; EXECUTION TIME; SOURCE CODES; TEMPLATES;

MULTIPROCESSING SYSTEMS;

EID: 24944566920     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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