Register constrained modulo scheduling

IEEE Transactions on Parallel and Distributed Systems

Volumn 15, Issue 5, 2004, Pages 417-430

  Zalamea, Javier ^a   Llosa, Josep ^a   Ayguadé, Eduard ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Instruction level parallelism; Instruction scheduling; Modulo scheduling; Register allocation; Spill code

Indexed keywords

CONSTRAINT THEORY; DIGITAL ARITHMETIC; HEURISTIC METHODS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; SCHEDULING; SHIFT REGISTERS; SOFTWARE ENGINEERING;

INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SCHEDULING; MODULO SCHEDULING; REGISTER ALLOCATION; SPILL CODE;

PARALLEL PROCESSING SYSTEMS;

EID: 3042632227     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2004.1278099     Document Type: Article

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