Full-speed field-programmable memory BIST architecture

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 1165-1173

  Xiaogang, Du ^a   Mukherjee, Nilanjan ^a   Cheng, Wu Tung ^a   Reddy, Sudhakar M ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESIGNS; FULL SPEED OPERATION; MARCH ALGORITHMS; MEMORY TESTING;

ALGORITHMS; AUTOMATIC TESTING; BUILT-IN SELF TEST; DIGITAL STORAGE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847096745     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584084     Document Type: Conference Paper

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