An industrial evaluation of DRAM Tests

IEEE Design and Test of Computers

Volumn 21, Issue 5, 2004, Pages 430-440

  van de Goor, Ad J ^a  

^a Department of Microelectronics   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; SEMICONDUCTOR DEVICE TESTING; THERMAL STRESS;

FAULT ANALYSIS; MEMORY TESTS; STRESS COMBINATION; TIMING STRESS; VOLTAGE STRESS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 7244226233     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.51     Document Type: Article

References (10)

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2. H.-D. Oberle and P. Muhmenthaler, "Test Pattern Development and Evaluation for DRAMs with Fault Simulator, RAMSIM," Proc. Int'l Test Conf. (ITC 91), IEEE CS Press, 1991, pp. 548-555.
3. A.J. van de Goor and G.N. Gaydadjiev, "March LR: A Memory Test for Realistic Linked Faults," Proc. 14th IEEE VLSI Test Symp. (VTS 96), IEEE CS Press, 1996, pp. 272-280.
4. A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, ComTex Publishing, 1998.
5. H. Goto, S. Nakamura, and K. Iwasaki, "Experimental Fault Analysis of 1Mb SRAM Chips," Proc. 15th IEEE VLSI Test Symp. (VTS 97), IEEE CS Press, 1997, pp. 31-36.
6. I. Schanstra and A.J. van de Goor, "An Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs," Proc. IEEE Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, pp. 983-992.
7. A.J. van de Goor and J. de Neef, "Industrial Evaluation of DRAM Tests," Proc. Design Automation and Test in Europe (DATE 99), IEEE CS Press, pp. 623-630.
8. A.J. van de Goor and A. Paalvast, "Industrial Evaluation of DRAM SIMM Tests," Proc. IEEE Int'l Test Conf. (ITC 00), IEEE CS Press, 1999, pp. 426-435.
9. A.J. van de Goor and I. Schanstra, "Address and Data Scrambling: Causes and Impact on Memory Tests," Proc. 1st IEEE Int'l Workshop on Electronic Design, Test and Application (DELTA 02), IEEE Press, 2002, pp. 128-136.
10. M. Klaus and A.J. van de Goor, "Tests for Resistive and Capacitive Defects in Address Decoders," Proc. 10th Asian Test Symp. (ATS 01), IEEE CS Press, 2001, pp. 31-36.