Bist for Deep Submicron ASIC Memories with High Performance Application

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 386-392

  Powell, Theo J ^a   Cheng, Wu Tung ^b   Rayhawk, Joseph ^b   Samman, Omer ^b   Policke, Paul ^a   Lai, Sherry ^a  

^a TEXAS INSTRUMENTS   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS;

MEMORY LAYOUT CODES;

RANDOM ACCESS STORAGE;

EID: 0142184808     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Rochit Rajsuman, "Design and Test of Large Embedded Memories: An overview", IEEE Design and Test of Computers, May-June 2001.
2. Ivo Schanstra, Dharmajaya Lukita, Ad J.van de Goor, Kees Veelenturf, Fault J.van Wijnen, "Semiconductor Manufacturing Process Monitoring Using Built-in Self-Test For Embedded Memories", pp. 872-881, IEEE International Test Conference, 1998.
3. A.J. van de Goor, "Testing Semiconductor Memories: Theory and Practice", John Wiley & Sons, Ltd., England, 1991.
4. A.J. van de Goor, "Using March tests to test SRAMs," IEEE Design & Test of Computers, 3/1993, pp. 8-13.
5. R. Dean Adams, "High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test", Kluwer, Massachusetts, Oct. 2002.
6. Mentor Graphics Corporation, "Built-in Self-Test Process Guide", Software Version 8.2002_2, June 2002.
7. Mentor Graphics Corporation, "MBISTArchitect Reference Manual", Software Version 8.2002_2, June 2002.
8. J.P. Hayes, "Testing memories for single-cell pattern-sensitive faults in semiconductor random-access memories", IEEE Trans. On Computers, Vol. C-29, No. 3, 1980. pp. 249-54.