Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2005, Issue , 2005, Pages 87-93

  Shih, Che Hua ^a   Huang, Juinn Dar ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL COMPUTERS; FINITE AUTOMATA; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; SYSTEMS ANALYSIS;

INTERFACE PROTOCOL; NON-DETERMINISTIC EXTENDED FINITE STATE MACHINE (NEFSM); SIMULATION STIMULI;

REPORT GENERATORS;

EID: 33846565403     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2005.1568819     Document Type: Conference Paper

References (21)

1. K. Shimizu, D. L. Dill, and A. J. Hu, "Monitor-based Formal Specification of PCI," Proceedings of the 3th International Conference on Formal Methods in Computer-Aided Design, pp.335-353, November 2000.
2. A. Nightingale and J. Goodenough, "Testing for AMBA™ Compliance," Proceedings of the 14th Annual IEEE International ASIC/SOC Conference, pp.301-305, September 2001.
3. M. T. Oliviera and A. J. Hu, "High Level Specification and Automatic Generation of IP Interface Monitors," Proceedings of the 39th Design Automation Conference, pp.129-134, June 2002.
4. A. J. Hu, J. Casus, and J. Yang, "Efficient Generation of Monitor Circuits for GSTE Assertion Graphs," Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp.154-159, November 2003.
5. A. Roychoudhury, T. Mitra, and S. R. Karri, "Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol," Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp.828-833, March 2003.
6. H-M. Lin, C-C. Yen, C-H. Shih, and J-Y. Jou, "On Compliance Test of On-Chip Bus for SOC," Proceedings of the Asia and South Pacific Design Automation Conference, pp.328-333, January 2004.
7. K. Ara and K. Suzuki, "A Proposal for Transaction-Level Verification with Component Wrapper Language," Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp.82-87, March 2003.
8. J. Yuan, K. Shultz, C. Pixley, H. Miller, and A. Aziz, "Modeling Design Constraints and Biasing in Simulation Using BDDs," Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, pp.584-589, November 1999.
9. K. Shimizu and D. L. Dill, "Deriving a Simulation Input Generator and a Coverage Metric From a Formal Specification," Proceedings of the 39th Design Automation Conference, pp.801-806, June 2002.
10. J. Yuan, A. Aziz, K. Albin, and C. Pixley, "Simplifying Boolean Constraint Solving for Random Simulation-Vector Generation," Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design, pp. 123-127, November 2002.
11. J. Yuan, K. Albin, A. Aziz, and C. Pixley, "Constraint Synthesis for Environment Modeling in Functional Verification," Proceedings of the 40th Design Automation Conference, pp.296-299, June 2003.
12. J. Yuan, C. Pixley, A. Aziz, and K. Albin, "A Framework for Constrained Functional Verification," Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp.142-145, November 2003.
13. M. A. Iyer, "RACE: A Word-level ATPG-based Constraints Solver System for Smart Random Simulation," Proceedings of the 2003 International Test Conference, pp.299-308, September 2003.
14. G. V. Bochmann and J. Gecsei, "A Unified Method for the Specification and Verification of Protocols," Proceeding of the International Federation for Information Processing Congress '77, pp.229-234, August 1977.
15. K-T. Cheng and A. S. Krishnakumar, "Automatic Functional Test Generation Using the Extended Finite State Machine Model," Proceedings of the 30th Design Automation Conference, pp.86-91, June 1993.
16. D. Lee and M. Yannakakis, "Optimization Problems from Feature Testing of Communication Protocols," Proceedings of the 4th International Conference on Network Protocols, pp.66-75, October 1996.
17. C. Besse, A. Cavalli, and D. Lee, "An Automatic and Optimized Test Generation Technique Applying to TCP/IP Protocols," Proceedings of the 14th International Conference on Automated Software Engineering, pp.73-80, October 1999.
18. ARM Limited, AMBA Specification (Rev. 2.0), May 1999.
19. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: John Wiley & Sons, Inc., 1987.
20. OpenCores Organization, Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores, Rev. B.3, September 2002.
21. http://www.opencores.org/.