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Volumn , Issue , 2003, Pages 142-145

A Framework for Constrained Functional Verification

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN UNDER VERIFICATION (DUV); MULTIPLE CLOCK DOMAINS;

EID: 0346148492     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (34)

References (17)
  • 1
    • 0020782108 scopus 로고
    • On the desirability of acyclic database schemes
    • C. Beeri, R. Fagin, D. Maier, and M. Yannakakis. On the desirability of acyclic database schemes. J. ACM, 30(3):479-513, 1983.
    • (1983) J. ACM , vol.30 , Issue.3 , pp. 479-513
    • Beeri, C.1    Fagin, R.2    Maier, D.3    Yannakakis, M.4
  • 5
    • 0025556059 scopus 로고
    • A Unified Framework for the Formal Verification of Sequential Circuits
    • November
    • O. Coudert and J. C. Madre. A Unified Framework for the Formal Verification of Sequential Circuits. In Proc. Intl. Conf. on Computer-Aided Design, pages 126-129, November 1990.
    • (1990) Proc. Intl. Conf. on Computer-aided Design , pp. 126-129
    • Coudert, O.1    Madre, J.C.2
  • 7
    • 0003000434 scopus 로고    scopus 로고
    • A comparison of structural csp decomposition methods
    • G. Gottlob, N. Leone, and F. Scarcello. A comparison of structural csp decomposition methods. IJCAI, 1999.
    • (1999) IJCAI
    • Gottlob, G.1    Leone, N.2    Scarcello, F.3
  • 8
    • 0028400405 scopus 로고
    • Decomposing Constraint Satisfaction Problems Using Database Techniques
    • M. Gyssens, P. Jeavons, and D. Cohen. Decomposing Constraint Satisfaction Problems Using Database Techniques. Artificial Intelligence, pages 57-89, 1994.
    • (1994) Artificial Intelligence , pp. 57-89
    • Gyssens, M.1    Jeavons, P.2    Cohen, D.3
  • 10
    • 0002755438 scopus 로고    scopus 로고
    • Integrating Model Checking into the Semiconductor Design Flow
    • March
    • C. Pixley. Integrating Model Checking Into the Semiconductor Design Flow. Computer Design 's Electronic Systems journal, pages 67-74, March 1999.
    • (1999) Computer Design 's Electronic Systems Journal , pp. 67-74
    • Pixley, C.1
  • 12
    • 0000673493 scopus 로고
    • Graph minors. II. Algorithmic aspects of tree-width
    • N. Robertson and P. D. Seymour. Graph minors, ii. algorithmic aspects of tree-width. Journal of Algorithms, pages 7:309-322, 1986.
    • (1986) Journal of Algorithms , vol.7 , pp. 309-322
    • Robertson, N.1    Seymour, P.D.2
  • 13
    • 0036048216 scopus 로고    scopus 로고
    • Deriving a simulation input generator and a coverage metric from a formal specification
    • June
    • Karma Shimizu and David Dill. Deriving a simulation input generator and a coverage metric from a formal specification. Proc. of the Design Automation Conf., pages 801-806, June 2002.
    • (2002) Proc. of the Design Automation Conf. , pp. 801-806
    • Shimizu, K.1    Dill, D.2
  • 14
    • 0021473698 scopus 로고
    • Simple linear-time algorithms to test chordality of graphs, test acyclicity of hypergraphs and selectively reduce acyclic hypergraphs
    • R. E. Tarjan and M. Yannakakis. Simple linear-time algorithms to test chordality of graphs, test acyclicity of hypergraphs and selectively reduce acyclic hypergraphs. SIAM J. Comput., 13(3):566-579, 1984.
    • (1984) SIAM J. Comput. , vol.13 , Issue.3 , pp. 566-579
    • Tarjan, R.E.1    Yannakakis, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.