Efficient Generation of Monitor Circuits for GSTE Assertion Graphs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 154-159

  Hu, Alan J ^a   Casas, Jeremy ^b   Yang, Jin ^b  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; COMPUTER SIMULATION; GRAPH THEORY; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

FORMAL DESIGN VERIFICATION; GENERALIZED SYMBOLIC TRAJECTORY EVALUATION (GSTE);

FORMAL LOGIC;

EID: 0346148498     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159685     Document Type: Conference Paper

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