A 65nm-node LSTP (Low Standby Power) poly-Si/a-Si/HfSiON transistor with high Ion-Istandby ratio and reliability

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 40-41

  Yasuda, Y ^a   Kimizuka, N ^a   Iwamoto, T ^b   Fujieda, S ^b   Ogura, T ^b   Watanabe, H ^b,b   Tatsumi, T ^b   Yamamoto, I ^a   Ito, K ^a   Yamagata, Y ^a   Imai, K ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; DIELECTRIC DEVICES; ELECTRON MOBILITY; HAFNIUM COMPOUNDS; OPTIMIZATION; POLYSILICON; RELIABILITY; SEMICONDUCTOR DOPING; STANDBY POWER SYSTEMS;

CHANNEL DOPING; GATE-ELECTRODES; LOW STANDBY POWER (LSTP); TRAP SITES;

TRANSISTORS;

EID: 4544268944     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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4. S. J. Doh et al., IEDM Tech. Digest, p.934, 2003.
5. A. Kaneko et al., SSDM proceeding, p.56, 2003.
6. C. B. Oh et al., VLSI Tech. Symp., p.71, 2003.