A fitting approach to generate symbolic expressions for linear and nonlinear analog circuit performance characteristics

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 268-273

  Daems, Walter ^a   Gielen, Georges ^a   Sansen, Willy ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIZING; GEOMETRIC PROGRAMMING; GOODNESS OF FIT; NONLINEAR ANALOG CIRCUITS; NONLINEAR CIRCUIT; SYMBOLIC EXPRESSION; TEMPLATE-BASED;

EXHIBITIONS;

NUMERICAL METHODS;

EID: 2342658458     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998283     Document Type: Conference Paper

References (32)

1. L. R. Carley, G. Gielen, R. A. Rutenbar, and W. Sansen, "Synthesis tools for mixed-signal ICs: Progress on frontend and backend strategies," in Proc. DAC, pp. 298-303, June 1996.
2. K. Singhal and J. Vlach, "Symbolic circuit analysis," Proc. IEE, vol. 128, pp. 81-86, Apr. 1981.
3. J. Starzyk and A. Konczykowska, "Flowgraph analysis of large electronic networks," IEEE Trans. on CAS, vol. 33, pp. 302-315, Mar. 1986.
4. A. Liberatore and S.Manetti, "SAPEC: A personal computer program for the symbolic analysis of electric circuits," in Proc. IEEE ISCAS, pp. 897-900, 1988.
5. S. J. Seda, G. R. Degrauwe, and W. Fichtner, "A symbolic analysis tool for analog circuit design automation," in Proc. IEEE/ACM ICCAD, pp. 488-491, 1988.
6. G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1587-1597, Dec. 1989.
7. F. V. Fernández-Fernandéz and A. Rodríguez- Vázquez, "Interactive AC modeling and characterization of analog circuits via symbolic analysis," Journal of Analog Integrated Circuits and Signal Processing, vol. 1, pp. 183-208, Nov. 1991.
8. R. Sommer, E. Hennig, G. Dröge, and E.-H. Horneber, "Equationbased symbolic approximation by matrix reduction with quantitative error prediction," Alta Frequenza-Rivista Di Elettronica, vol. 5, pp. 317-325, Dec. 1993.
9. Q. Yu and C. Sechen, "Approximate symbolic analysis of large analog integrated circuits," in Proc. IEEE/ACM ICCAD, pp. 664-671, 1994.
10. P. Wambacq, F. V. Fernández-Fernandéz, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, "Efficient symbolic computation of approximated small-signal characteristics," IEEE Journal of Solid-State Circuits, vol. 30, pp. 327-330, Mar. 1995.
11. C.-J. R. Shi and X.-D. Tan, "Symbolic analysis of large analog circuits with determinant decision diagrams," in Proc. IEEE/ACM ICCAD, Nov. 1997.
12. O. Guerra, J. D. Rodríguez-García, E. Roca, F. V. Fernández-Fernandéz, and A. Rodríguez-Vázquez, "A simplification before and during generation methodology for symbolic large-circuit analysis," in Proc. ICECS, vol. 3, pp. 81-84, Sept. 1998.
13. W. Daems, G. Gielen, and W. Sansen, "Circuit complexity reduction for symbolic analysis of analog integrated circuits," in Proc. DAC, pp. 958-963, June 1999.
14. W. Verhaegen and G. Gielen, "Efficient DDD-based symbolic analysis of large linear analog circuits," in Proc. DAC, pp. 139-144, June 2001.
15. M. M. Hassoun and K. S. McCarville, "Symbolic analysis of largescale networks using a hierarchical signal flowgraph approach," Journal of Analog Integrated Circuits and Signal Processing, no. 3, pp. 31-42, 1993.
16. M. Pierzchala and B. Rodanski, "Symbolic analysis of large-scale networks by circuit reduction to a two-port," in Proc. SMACD Workshop, Oct. 1996.
17. O. Guerra, J. D. Rodríguez-García, E. Roca, F. V. Fernández-Fernandéz, and A. Rodríguez-Vázquez, "True hierarchical symbolic analysis of large-scale analog integrated circuits.," in Proc. SMACD Workshop, pp. 164-168, Oct. 1998.
18. G. Dröge and E.-H. Horneber, "Symbolic calculation of poles and zeros," in Proc. SMACD Workshop, 1996.
19. G. Nebel, U. Kleine, and H. Pfleiderer, "Symbolic pole/zero calculation using SANTAFE," IEEE Journal of Solid-State Circuits, vol. 30, pp. 752-761, July 1995.
20. J. J. Hsu and C. Sechen, "Accurate extraction of simplified symbolic pole/zero expressions for large analog ICs," in Proc. IEEE ISCAS, pp. 2083-2087, 1995.
21. F. Constantinescu and M. Nitescu, "A new approach to symbolic pole computation," in Proc. ECCTD, pp. 665-658, 1995.
22. J. D. Rodríguez-García, O. Guerra, F. V. Fernández-Fernandéz, and A. Rodríguez-Vázquez, "A symbolic pole/zero extraction methodoly based on analysis of circuit time-constants," in Proc. DCIS, pp. 327-332, 1999.
23. P. Wambacq, G. Gielen, P. R. Kinget, and W. Sansen, "Highfrequency distortion analysis of analog integrated circuits," IEEE Trans. on CAS-II: Analog and Digital Signal Processing, vol. 46, pp. 335-345, Mar. 1999.
24. W. Verhaegen and G. Gielen, "Symbolic distortion analysis of analog integrated circuits," in Proc. ECCTD, Aug. 2001.
25. R. J. Duffin, C. Zener, and E. L. Peterson, Geometric programming: theory and application. New York: John Wiley & Sons, 1967.
26. M. Hershenson, S. P. Boyd, and T. H. Lee, "Optimal design of a CMOS op-amp via geometric programming," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 1-21, Jan. 2001.
27. P. Mandal and V. Visvanathan, "CMOS op-amp sizing using a geometric programming formulation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 22-38, Jan. 2001.
28. K. O. Kortanek, X. Xu, and Y. Ye, "An infeasible interior-point algorithm for solving primal and dual geometric programs," Math. Programming, vol. 76, pp. 155-181, 1996.
29. W. Daems, G. Gielen, and W. Sansen, "Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuits," in Proc. IEEE/ACM ICCAD, pp. xx-xx, Nov. 2001.
30. G. E. P. Box, W. G. Hunter, and J. S. Hunter, Statistics for experimenters: an introduction to design, analysis and model building. New York: John Wiley & Sons, 1978.
31. A. S. Hedayat, S. N. J. A., and J. Stufken, Orthogonal arrays: theory and applications. New York: Springer-Verlag, 1999.
32. F. Leyn, G. Gielen, and W. Sansen, "An efficient dc root solving algoritm with guaranteed convergence for analog integrated cmos circuits," in Proc. IEEE/ACM ICCAD, pp. 304-307, Nov. 1998.