The sizing rules method for analog integrated circuit design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 343-349

  Graeb, H ^a   Zizala, S ^a   Eckmueller, J ^a   Antreich, K ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; HIERARCHICAL SYSTEMS;

INTEGRATED CIRCUIT DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035208990     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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