An analog silicon retina with multichip configuration

IEEE Transactions on Neural Networks

Volumn 17, Issue 1, 2006, Pages 197-210

  Kameda, Seiji ^a,b   Yagi, Tetsuya ^a  

^a OSAKA UNIVERSITY   (Japan)

^b HIROSHIMA UNIVERSITY   (Japan)

Author keywords

Analog VLSI; Multichip; Neuromorphic sensor; Real time image processing; Robot vision; Silicon retina

Indexed keywords

COMPUTER VISION; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SENSORS; VLSI CIRCUITS;

MULTICHIP CONFIGURATION; NEUROMORPHIC SENSOR; NEUROMORPHIC SILICON RETINA; REAL TIME IMAGE PROCESSING; SAMPLE/HOLD CIRCUITS; SILICON RETINA;

IMAGE PROCESSING;

ALGORITHM; ANALOG COMPUTER; ARTICLE; AUTOMATED PATTERN RECOGNITION; ELECTRONICS; MICROCOMPUTER; PHYSIOLOGY; RETINA; VISUAL PROSTHESIS;

ALGORITHMS; COMPUTERS, ANALOG; ELECTRONICS; EYE, ARTIFICIAL; MICROCOMPUTERS; PATTERN RECOGNITION, AUTOMATED; RETINA;

EID: 33144481291     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2005.860867     Document Type: Article

References (41)

1. S. Kameda and T. Yagi, "An analog VLSI chip emulating sustained and transient response channels of the vertebrate retina," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1405-1412, Oct. 2003.
2. C. Koch and H. Li, Eds., Vision Chips: Implementing Vision Algorithms with Analog VLSI Circuits. Los Alamitos, CA: IEEE Comput. Soc. Press, 1995.
3. C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, 1989.
4. A. Moini, Vision Chips. Norwell, MA: Kluwer, 2000.
5. R. C. Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, T. Roska, C. Rekeczky, I. Petrás, and A. Rodríguez-Vázquez, "A bio-inspired two-layer mixed-signal flexible programmable chip for early vision," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1313-1336, Oct. 2003.
6. K. A. Boahen, "A retinomorphic chip with parallel pathways: Encoding on, off, increasing, and decreasing visual signals," J. Analog Integr. Circuits Signal Process., vol. 30, no. 2, pp. 121-135, 2002.
7. T. Y. W. Choi, B. E. Shi, and K. A. Boahen, "An on-off orientation selective address event representation image transceiver chip," IEEE Trans. Circuits Systs. I, Reg. Papers, vol. 51, no. 2, pp. 342-353, Feb. 2004.
8. S.-C. Liu and R. Douglas, "Temporal coding in a silicon network of integrate-and-fire neurons," IEEE Trans. Neural Netw., vol. 15, no. 5, pp. 1305-1314, Oct. 2004.
9. C. M. Higgins and S. A. Shams, "A biologically inspired modular VLSI system fo visual measurement of self-motion," IEEE Sensors. J, vol. 2, no. 6, pp. 508-528, Dec. 2002.
10. D. H. Gordberg, G. Cauwenberghs, and A. G. Andreou, "Probabilistic synapses weighting in a reconfigurable network of VLSI integrate-and-fire neurons," Neural Netw., vol. 14, pp. 781-793, 2001.
11. G. Indiveri, R. Murer, and J. Kramer, "Active vision using an analog VLSI model of selective attention," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 48, no. 5, pp. 492-500, May 2001.
12. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbrück, T. Burg, and R. Douglas, "Orientation-selective a VLSI spiking neurons," Neural Netw., vol. 14, pp. 629-643, 2001.
13. P. Venier, A. Mortara, X. Arreguit, and E. A. Vittoz, "An integrated cortical layer for orientation enhancement," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 177-186, Feb. 1997.
14. K. A. Boahen, "Point-to-Point connectivity between neuromorphic chips using address-events," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 47, no. 5, pp. 416-434, May 2000.
15. M. Mahowald, An Analog VLSI System for Stereoscopic Vision. Norwell, MA: Kluwer, 1994.
16. W. Maass and C. M. Bishop, Eds., Pulsed Neural Networks. London, U.K.: The MIT Press, 2001.
17. M. Sivilotti, "Wiring Considerations in Analog VLSI systems, with Applications to Field-Programmable Networks," California Inst. Technol., Pasadena, 1991.
18. T. Yagi, F. Ariki, and Y. Funabashi, "Dynamic model of dual layer neural network for vertebrate retina," in Proc. Int. Joint Conf. Neural Netw., vol. 1, 1989, pp. 787-789.
19. T. Yagi, S. Ohshima, and Y. Funahashi, "The role of retinal bipolar cell in early vision: An implication with analogue networks and regularization theory," Biol. Cybern., vol. 77, pp. 163-171, 1997.
20. S.-Y. Ma and L.-G. Chen, "A single-chip CMOS APS camera with direct frame difference output," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1415-1418, Oct. 1999.
21. S. K. Mendis, E. Sabrina, R. C. Gee, B. Pain, C. O. Staller, Q. Kim, and E. R. Fossum, "CMOS active pixel image sensors for highly integrated imaging systems," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 187-197, Feb. 1997.
22. H. Kobayashi, T. Matsumoto, T. Yagi, and K. Tanaka, "Light-Adaptive architectures for regularization vision chips," Neural Netw., vol. 8, no. 1, pp. 87-101, 1995.
23. S. Kameda, A. Honda, and T. Yagi, "Real time image processing with an analog vision chip system," Int. J. Neural Syst., vol. 9, no. 5, pp. 423-428, 1999.
24. T. Sibano, K. Iizuka, M. Miyamoto, M. Osaka, R. Miyama, and A. Kito, "Matched filter for DS-CDMA of up to 50 MChip/s based on sampled analog signal processing," Proc. ISSCC Dig. Tech. Papers, pp. 100-101, 1997.
25. H. Kobayashi, T. Matsumoto, T. Yagi, and T. Shimmi, "Image processing regularization filters on layered architecture," Neural Netw., vol. 6, pp. 327-350, 1993.
26. C. N. Anagnostopoulos, T.-H. Lee, B. C. Burkey, and J. P. Lavine, "Block Readable Charge Coupled Device," U.S. Patent 4 330 796, May 18, 1982.
27. T. Yagi, S. Kameda, and K. Iizuka, "A parallel analog intelligent vision sensor with a variable receptive field," Syst. Comput. Jpn., vol. 30, no. 1, pp. 60-69, 1999.
28. T. Shigematsu and M. Yamada, "Effects of dopamine on spatial properties of horizontal cells in the carp retina," Neurosci. Res., vol. Suppl. 8, pp. s69-s80, 1988.
29. J. Bastos, M. Steyaert, R. Rovers, P. Kinget, W. Sansen, B. Graindourze, A. Pergoot, and E. Janssens, "Mismatch characterization of small size MOS transistors," in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 8, 1995, pp. 271-276.
30. A. Pavasovic, A. G. Andreou, and C. R. Westgate, "Characterization of subthreshold MOS mismatch in transistors for VLSI systems," J. VLSI Signal Process., vol. 8, pp. 75-85, 1994.
31. P. W. Fry, P. J. W. Noble, and R. J. Rycroft, "Fixed-Pattern noise in photomatrices," IEEE J. Solid-State Circuits, vol. JSSC-5, no. 5, pp. 250-254, May 1970.
32. A. Simoni, G. Torelli, F. Maloberiti, A. Sartori, S. Plevridis, and A. Birbas, "A single-chip optical sensor with analog memory for motion detection," IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 800-806, Jul. 1995.
33. I. E. Abdou and W. K. Pratt, "Quantitative design and evaluation of enhancement/thresholding edge detectors," Proc. IEEE, vol. 67, no. 5, pp. 753-763, May 1979.
34. S.-C. Liu, "Silicon photoreceptors with controllable adaptive filtering properties," in Learning on Silicon: Adaptive Vlsi Neural Systems, G. Cauwenberghs and M. A. Bayoumi, Eds. Norwell, MA: Kluwer, 1999, pp. 67-78.
35. T. Delbrück and C. A. Mead, "Analog VLSI phototransduction by continuous-time, adaptive, logarithmic photoreceptor circuits," in Vision Chips: Implementing Vision Algorithms with Analog VLSI Circuits, C. Koch and H. Li, Eds. Los Alamitos, CA: IEEE Comput. Soc. Press, 1995, pp. 139-161.
36. D. J. Field, "Relations between the statistics of natural images and the response properties of cortical cells," J. Opt. Soc. Amer. A, vol. 4, no. 12, pp. 2379-2394, 1987.
37. S. Kameda and T. Yagi, "A silicon retina system that calculates direction of motion," in Proc. IEEE Int. Symp. Circuits and Systems, vol. IV, 2003, pp. 792-795.
38. C. Nakajima, M. Pontil, B. Heisele, and T. Poggio, "Full-body person recognition system," Pattern Recognition, vol. 36, pp. 1997-2006, 2003.
39. M. Yagi and T. Shibata, "An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1144-1161, May 2003.
40. M. Lades, J. C. Vorbrüggen, J. Buhmann, J. Lange, C. V. D. Malsburg, R. P. Würtz, and W. Konen, "Distortion invariant object recognition in the dynamic link architecture," IEEE Trans. Comput., vol. 42, no. 3, pp. 300-311, Mar. 1993.
41. Translated From Denshi Joho Tsushin Gakkai Ronbunshi, vol. J81-D-I, no. 2, pp. 104-113, 1998.