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Volumn 100, Issue 12, 2006, Pages

A paradigm for interconnect geometry to reduce grain boundary resistance

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL TRANSPORT; GEOMETRICAL PARAMETERS; SIDEWALL ROUGHNESS;

EID: 33846089350     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2401309     Document Type: Article
Times cited : (5)

References (19)
  • 4
    • 33846048200 scopus 로고    scopus 로고
    • International technology roadmap for semiconductors
    • International Technology Roadmap for Semiconductors, 2004, Interconnect Highlights and Table 80.
    • (2004) Interconnect Highlights and Table 80


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.