Single-grain Si TFTs and circuits inside location-controlled grains fabricated using a capping layer of SiO2

IEEE Transactions on Electron Devices

Volumn 54, Issue 1, 2007, Pages 124-130

  Rana, Vikas ^a   Ishihara, Ryoichi ^a   Hiroshima, Yasushi ^b   Inoue, Satoshi ^b   Shimoda, Tatsuya ^b   Metselaar, Wim ^c   Beenakker, Kees ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b SEIKO EPSON CORPORATION   (Japan)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Capping layer (C L) of SiO2; CMOS inverter; Excimer laser; Location control; Thin film transistor (TFT)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; EXCIMER LASERS; FIELD EFFECT SEMICONDUCTOR DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR INSULATOR BOUNDARIES;

CAPPING LAYER; GATE INSULATOR; LOCATION-CONTROLLED GRAIN; PROPAGATION GATE DELAY;

THIN FILM TRANSISTORS;

EID: 33846070969     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.887516     Document Type: Article

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