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Volumn 5, Issue 4-5, 2006, Pages 445-451

Silicon nanowires formation in CMOS compatible manner

Author keywords

CMOS; Sensors; Silicon nanowire; Vertically aligned

Indexed keywords

BIOSENSORS; CMOS INTEGRATED CIRCUITS; FABRICATION; PLASMA ETCHING; SILICON WAFERS; TRANSISTORS;

EID: 33845672175     PISSN: 0219581X     EISSN: None     Source Type: Journal    
DOI: 10.1142/s0219581x06004619     Document Type: Conference Paper
Times cited : (2)

References (20)
  • 10
    • 33845670158 scopus 로고    scopus 로고
    • US patent application publication # US 2002/0001977 A1
    • US patent application publication # US 2002/0001977 A1.
  • 11
    • 33845635391 scopus 로고    scopus 로고
    • US patent application publication # US 2003/0189202 A1
    • US patent application publication # US 2003/0189202 A1.
  • 17
    • 33845630011 scopus 로고    scopus 로고
    • World IP Organization Patent # WO 2004/003535 A1
    • World IP Organization Patent # WO 2004/003535 A1.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.