A novel delay fault testing methodology using low-overhead built-in delay sensor

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2934-2943

  Ghosh, Swaroop ^b   Bhunia, Swarup ^a,c   Raychowdhury, Arijit ^a,b,c   Roy, Kaushik ^a,b,c  

^a IEEE

^b PURDUE UNIVERSITY   (United States)

^c Case Western Reserve University   (United States)

Author keywords

Built in delay sensor (BIDS); Built in self test (BIST); Delay fault testing; Segment delay fault; Test point insertion; Transition delay fault

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; DELAY CIRCUITS; MICROPROCESSOR CHIPS; SENSORS;

BUILT IN DELAY SENSOR (BIDS); DELAY FAULT TESTING; LOGIC BLOCKS; SEGMENT DELAY FAULT; TEST POINT INSERTION; TRANSITION DELAY FAULT;

INTEGRATED CIRCUIT TESTING;

EID: 33845653669     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882523     Document Type: Article

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