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Volumn 2, Issue , 2004, Pages 1296-1301

Hybrid delay scan: A low hardware overhead scan-based delay test technique for high fault coverage and compact test sets

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT TEST SETS; DELAY TESTING; FAULT COVERAGES; HYBRID DELAY SCAN; BENCHMARK CIRCUIT; FAST SWITCHING; HARDWARE OVERHEADS; HYBRID APPROACH; HYBRID DELAYS; TRANSITION DELAY FAULTS;

EID: 3042845426     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (82)

References (13)
  • 4
    • 0019543877 scopus 로고
    • An implicit enumeration algorithm to generate tests for combinational logic circuits
    • Mar.
    • P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Trans. on Computers, Vol. C-30(3), Mar. 1981.
    • (1981) IEEE Trans. on Computers , vol.C-30 , Issue.3
    • Goel, P.1
  • 5
    • 0018809498 scopus 로고
    • Test generation & dynamic compaction of tests
    • P. Goel and B. C. Rosales. Test Generation & Dynamic Compaction of Tests. In Dig. Papers Test Conference, pages 182-192, 1979.
    • (1979) Dig. Papers Test Conference , pp. 182-192
    • Goel, P.1    Rosales, B.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.