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Volumn , Issue , 2002, Pages 138-147

Test point insertion that facilitates ATPG in reducing test time and data volume

Author keywords

ATPG; Compact test sets; Fault coverage; Gate delay faults; Stuck at faults; Test length; Test point insertion

Indexed keywords

ALGORITHMS; DATA REDUCTION; FUNCTIONS; NETWORKS (CIRCUITS);

EID: 0036443212     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (49)

References (15)
  • 4
    • 0030404034 scopus 로고    scopus 로고
    • Constructive multi-phase test point insertion for scan-based BIST
    • N. Tamarapalli, and J. Rajski. "Constructive Multi-Phase Test Point Insertion for Scan-Based BIST". Proc. of the IEEE Int. Test Conf., pp. 649-658, 1996.
    • (1996) Proc. of the IEEE Int. Test Conf. , pp. 649-658
    • Tamarapalli, N.1    Rajski, J.2
  • 7
    • 0016080118 scopus 로고
    • Test point placement to simplify fault detection
    • July
    • J.P. Hayes and A.D. Friedman. "Test Point Placement to Simplify Fault Detection". IEEE Trans. on Computers, C-33, pp. 727-735, July 1974.
    • (1974) IEEE Trans. on Computers , vol.C-33 , pp. 727-735
    • Hayes, J.P.1    Friedman, A.D.2
  • 9
    • 0029546834 scopus 로고
    • Timing-driven test point insertion for full-scan and partial-scan BIST
    • K.-T. Cheng and C-J. Lin, "Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST". Proc. of the IEEE Int. Test Conf., pp. 506-514, 1995.
    • (1995) Proc. of the IEEE Int. Test Conf. , pp. 506-514
    • Cheng, K.-T.1    Lin, C.-J.2
  • 15


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.