Optimal reconfiguration sequence management [FPGA runtime reconfiguration]

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 359-365

  Ghiasi, S ^a   Sarrafzadeh, M ^a  

^a Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); STRUCTURAL DESIGN;

CONTEXT SWITCHING; MODEL AND ALGORITHMS; MULTI-FPGA SYSTEM; OPTIMAL RECONFIGURATIONS; RECONFIGURABLE FABRICS; RECONFIGURABLE PLAT-FORMS; RECONFIGURABLE SYSTEMS; RUN TIME RECONFIGURATION;

RECONFIGURABLE HARDWARE;

EID: 33845535510     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195041     Document Type: Conference Paper

References (18)

1. L. Belady, "A Study of Replacement Algorithms for Virtual-Storage Computer", IBM Systems Journal, vol 5, no 2, pp. 78-101, 1966
2. A. DeHon, J. Wawrzynek, "Reconfigurable Computing: What, Why, Design Automation Requirements" Design Automation Conference, 1999.
3. A. DeHon. "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century". In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1994.
4. D. Taylor, J. Turner, J. Lockwood, E. Horta, "Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers", Computer Networks, vol. 38, no. 3, pp. 295-310, Feb 2002.
5. S. Sezer, J. Heron, R. Woods, R. Turner, A. Marshall, "Fast Partial Reconfiguration for FCCMs", IEEE Symposium on for Custom Computing Machines, 1998.
6. J. Burns, A. Donlin, J. Hogg, S. Singh, M. Wit. "A Dynamic Reconfiguration Run-Time System", IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
7. A. Adario, E. Roehe, S. Bampi, "Dynamically Reconfigurable Architecture for Image Processor Applications", Design Automation Conference, 1999.
8. J. Hauser, J. Wawrzynek, "Garp: A MIPS Processor with a Reconfigurable Coprocessor", IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 1997.
9. Xilinx Inc. online documentaion, http://www.xilinx.com/.
10. S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M. Sarrafzadeh. "A Super-Scheduler for Embedded Reconfigurable Systems", International Conference on Computer-Aided Design (ICCAD), November 2001.
11. P. Schaumont, I. Verbauwhede, K. Keutzer, M. Sarrafzadeh, "A Quick Safari through the Reconfigurable Jungle", Design Automation Conference, 2001.
12. Altera Inc. online documentaion, http://www.altera.com/
13. E. Horta, J. Lockwood, D. Taylor, D. Parlour, "Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration", Design Automation Conference, 2002
14. Z. Li, S. Hauck, "Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 187-195, 2002
15. Z. Li, S. Hauck, "Configuration Compression for Virtex FPGAs", IEEE Symposium on FPGAs for Custom Computing Machines, 2001.
16. Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for FPGAs", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 22-36, 2000
17. K. Compton, S. Hauck, "Reconfigurable Computing: A Survey of Systems and Software", ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002.
18. Z. Li, K. Compton, S. Hauck, "Configuration Caching Management Techniques for Reconfigurable Computing", Symposium on Field-Programmable Custom Computing Machines, 2000.