Timing-aware power noise reduction in layout

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 627-634

  Yeh, Chao Yang ^a   Marek Sadowska, Malgorzata ^b  

^a Apache Design Solutions ^*

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; LINEAR PROGRAMMING; NATURAL FREQUENCIES; NOISE ABATEMENT;

DECAP PADDINGS; GATE SIZING; SWITCHING CELLS; SWITCHING FREQUENCY;

INTEGRATED CIRCUIT LAYOUT;

EID: 33751414786     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560143     Document Type: Conference Paper

References (10)

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