메뉴 건너뛰기




Volumn , Issue , 2001, Pages 167-172

Automated power supply noise reduction via optimized distributed capacitors insertion

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT INTERCONNECTS; JITTER; RECONFIGURABLE HARDWARE;

EID: 84963800476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2001.914959     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 1
    • 85088084269 scopus 로고    scopus 로고
    • Analysis and performance Impact Caused by Power Supply Noise in Deep Submicron Devices
    • Y.M. Jiang, K.T.Cheng, "Analysis and performance Impact Caused by Power Supply Noise in Deep Submicron Devices" in DAC99, San Francisco, Ca., USA.
    • DAC99, San Francisco, Ca., USA
    • Jiang, Y.M.1    Cheng, K.T.2
  • 2
    • 0030704451 scopus 로고    scopus 로고
    • Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
    • H. Chen, D. Ling, "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design", DAC 1997.
    • DAC 1997
    • Chen, H.1    Ling, D.2
  • 3
    • 0032637991 scopus 로고    scopus 로고
    • A statistical Noise-Tolerance Analysis and Test Structure for logic families
    • Goteborg, Sweden, March 14-16
    • M. Graziano, G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni "A statistical Noise-Tolerance Analysis and Test Structure for logic families", ICMTS99, Goteborg, Sweden, March 14-16, 1999.
    • (1999) ICMTS99
    • Graziano, M.1    Masera, G.2    Piccinini, G.3    Ruo Roch, M.4    Zamboni, M.5
  • 5
    • 0034483875 scopus 로고    scopus 로고
    • Fast analysis and optimization of power/ground networks
    • San Jose, CA, USA
    • H. S., K. Gala, and S. S. Sapatnekar, 'Fast analysis and optimization of power/ground networks," in Proc. of ICCAD00, (San Jose, CA, USA), 2000.
    • (2000) Proc. of ICCAD00
    • S, H.1    Gala, K.2    Sapatnekar, S.S.3
  • 9
    • 0032636952 scopus 로고    scopus 로고
    • Getting to the Bottom of Deep Submicron II: A global wiring paradigm
    • D. Sylvester, K. Keutzer, "Getting to the Bottom of Deep Submicron II: a global wiring paradigm" in ISPD99, Monterey, Ca., USA.
    • ISPD99, Monterey, Ca., USA
    • Sylvester, D.1    Keutzer, K.2
  • 10
    • 0033697723 scopus 로고    scopus 로고
    • On-Chip Decoupling Capacitor Optimization usign Architectural Level Current Signature Prediction
    • M. Pant and P. Pant and D.S. Willis "On-Chip Decoupling Capacitor Optimization usign Architectural Level Current Signature Prediction", ASIC/SOC 2000, Arlington, VA, September 2000
    • ASIC/SOC 2000, Arlington, VA, September 2000
    • Pant, M.1    Pant, P.2    Willis, D.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.