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Volumn , Issue , 2004, Pages 305-308

A new multi-channel on-chip-bus architecture for system-on-chips

Author keywords

Crossbar router; Efficient Bandwidth; Multi channel; Multi master; On chip bus; SoC Bus; SoC, SNA

Indexed keywords

BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; DATA PROCESSING; DATA TRANSFER; DECODING; DIES; ENCODING (SYMBOLS); MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; ROUTERS; SEMICONDUCTING SILICON;

EID: 14844286882     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (16)

References (11)
  • 5
    • 85059049322 scopus 로고    scopus 로고
    • HERMES: An infrastructure for low area overhead packet-switching networks on chip
    • accepted for publication
    • F. MORAES, N. CALAZANS, et al., "HERMES:an Infrastructure for Low Area Overhead Packet-switching Networks on Chip," Integration, the VLSI Journal (accepted for publication).
    • Integration, the VLSI Journal
    • Moraes, F.1    Calazans, N.2
  • 11
    • 14844287875 scopus 로고    scopus 로고
    • Hantro Products OY, http://www.hantro.com/pdf/overview.pdf.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.