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Volumn , Issue , 2004, Pages 305-308
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A new multi-channel on-chip-bus architecture for system-on-chips
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Author keywords
Crossbar router; Efficient Bandwidth; Multi channel; Multi master; On chip bus; SoC Bus; SoC, SNA
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Indexed keywords
BANDWIDTH;
COMMUNICATION CHANNELS (INFORMATION THEORY);
COMPUTER SIMULATION;
DATA PROCESSING;
DATA TRANSFER;
DECODING;
DIES;
ENCODING (SYMBOLS);
MULTIPROCESSING SYSTEMS;
PROGRAM PROCESSORS;
ROUTERS;
SEMICONDUCTING SILICON;
CROSSBAR ROUTERS;
EFFICIENT BANDWIDTH;
MULTI-CHANNELS;
MULTI-MASTER;
ON-CHIP-BUS;
SOC;
SOC NETWORK ARCHITECTURE (SNA);
SYSTEM-ON-CHIP (SOC) BUSES;
INTEGRATED CIRCUIT LAYOUT;
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EID: 14844286882
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (16)
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References (11)
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