Future trends in SoC interconnect

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)

Volumn 2005, Issue , 2005, Pages 295-298

  Furber, Steve ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER SOFTWARE; HIERARCHICAL SYSTEMS; INTERCONNECTION NETWORKS; LARGE SCALE SYSTEMS; PACKET NETWORKS; PROBLEM SOLVING; PRODUCTIVITY; REUSABILITY; TIME DOMAIN ANALYSIS;

ISOLATED TIMING DOMAIN; SELF-TIMED PACKET-SWITCHED NETWORKS; SYSTEMS ON CHIP (SOC); TIMING CLOSURE PROBLEMS;

MICROPROCESSOR CHIPS;

EID: 33745465551     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2005.1500079     Document Type: Conference Paper

References (6)

1. J.D. Garsids, W.J. Bainbridge, A. Bardsley, D.M. Clark, D.A. Edwards, S.B. Furber, J. Liu, D.W. Lloyd, S. Mohammadi, J.S. Pepper, O. Petlin, S. Temple, & J.V. Woods, "AMULET3i - an Asynchronous System-on-Chip", Proc. Async 2000, Eilat, Israel, 4-6 April 2000, pp 162-175.
2. W.J. Bainbridge & S.B. Furber, "MARBLE: An Asynchronous On-Chip Macrocell Bus", Microprocessors and Microsystems, 24(4), 1 August 2000, pp. 213-222.
3. W.J. Dally & B. Towles, "Route Packets, not Wires: On-Chip Interconnection Networks", Proc. DAC 2001, ACM Press, New York, 2001, pp. 684-689.
4. W.J. Bainbridge & S.B. Furber, "Chain: A Delay-Insensitive Chip Area Interconnect", IEEE Micro, special issue on the Design and Test of System-on-Chip 22(5), September/October 2002, pp. 16-23.
5. W.J. Bainbridge, L.A. Plana & S.B. Furber, "The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip", Proc. DATE'04, Vol. 3, Paris, Feb 2004, p. 274.
6. T. Felicijan & S.B. Furber, "An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support", Proc. IEEE International SOC Conference, Santa Clara, CA, Sept. 2004, pp. 274-277.