Support for partial run-time reconfiguration of platform FPGAs

Journal of Systems Architecture

Volumn 52, Issue 12, 2006, Pages 709-726

  Silva, Miguel L ^a   Ferreira, João Canas ^a,b  

^a UNIVERSITY OF PORTO   (Portugal)

^b UNIVERSITY OF PORTO   (Portugal)

Author keywords

Bitstream manipulation; Partial reconfiguration; Platform FPGA; Run time reconfiguration; Run time support system

Indexed keywords

COMPUTER HARDWARE; DATA STRUCTURES; EMBEDDED SYSTEMS; IMAGE ANALYSIS; INTEGRATED CIRCUITS; PATTERN MATCHING; SOFTWARE ENGINEERING;

BITSTREAM MANIPULATION; PARTIAL RECONFIGURATION; PLATFORM FPGA; RUN TIME RECONFIGURATION; RUN TIME SUPPORT SYSTEM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33750626253     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2006.04.004     Document Type: Article

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