RAPID for high-performance computing systems: Architecture and performance evaluation

Applied Optics

Volumn 45, Issue 25, 2006, Pages 6326-6334

  Kodi, Avinash Karanth ^a   Louri, Ahmed ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DISTRIBUTED COMPUTER SYSTEMS; OPTICAL INTERCONNECTS; THROUGHPUT; TRANSMITTERS;

BANDWIDTH DENSITY; HIGH PERFORMANCE COMPUTING SYSTEMS (HPCS); NETWORK LATENCY; PERFORMANCE EVALUATION;

COMPUTER SYSTEMS;

EID: 33750365512     PISSN: 1559128X     EISSN: 15394522     Source Type: Journal    
DOI: 10.1364/AO.45.006326     Document Type: Article

References (25)

1. A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, "Exploitation of optical interconnects in future server architectures," IBM J. Res. Dev. 49, 755-775 (2005).
2. E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, "Optical interconnect system integration for ultra-short-reach applications," Intel Technol. J. 8, 114-127 (2004).
3. D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach (Morgan Kaufmann, 1999).
4. T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, "Optical interconnects: out of the box forever?" IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
5. B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Madhavan, A. F. J. Levi, and D. W. Dolfi, "MAUI: enabling fiber-to-the-processor with parallel multiwavelength optical interconnects," J. Lightwave Technol. 22, 2043-2054 (2004).
6. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE 88, 728-749 (2000).
7. J. Collet, D. Litaize, J. V. Campenhut, C. Jesshope, M. Desmulliez, H. Thienpont, J. Goodman, and A. Louri, "Architectural approaches to the role of optics in mono and multiprocessor machines," Appl. Opt., 39, 671-682 (2000).
8. J. Higgins, "Building secure Sun fire link interconnect networks using midframe servers," Sun MicroSystems, Sun BluePrints Online, 2003, http://www.sun.com/blueprints/0203/817-1656.pdf 817-1656.
9. A. K. Kodi and A. Louri, "RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors," J. Lightwave Technol. 22, 2101-2110 (2004).
10. Intel Corporation White Paper; PCI Express Ethernet Networking, Technical Rep. 254108-002 (Intel Corporation, 2003).
11. Hyper Transport Technology I/O Link, Technical Rep. 25012A (Advanced Micro Devices, 2001).
12. A. V. Krishnamoorthy and K. W. Goossen, "Optoelectronic-VLSI: photonic integrated with VLSI circuits," IEEE J. Sel. Top. Quantum Electron. 4, 899-912 (1998).
13. M. Arai, T. Kondo, A. Matsutani, T. Miyamoto, and F. Koyama, "Growth of highly strained GaInAs-GaAa quantum wells on patterned substrate and its application for multiple-wavelength vertical-cavity surface-emitting laser array," IEEE J. Sel. Top. Quantum Electron. 8, 811-816 (2002).
14. L. Eldada and L. W. Shacklette, "Advances in polymer integrated optics," IEEE J. Sel. Top. Quantum Electron. 6, 54-68 (2000).
15. M. K. Smit, "PHASAR-based WDM devices: principles, design and applications," IEEE J. Sel. Top. Quantum Electron. 2, 236-250 (1996).
16. C. Dragone, "An N × N optical multiplexer using a planar arrangement of two star couplers," IEEE Photon. Technol. Lett. 3, 1073-1075 (1991).
17. A. V. Krishnamoorthy, K. Gossen, L. Chirovsky, R. Rozier, P. Chandramani, S. Hui, J. Lopata, J. Walker, and L. A. D'Asaro, "16 × 16 VCSEL array flip-chip bonded to CMOS VLSI circuit," IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
18. Y. Liu, L. Lin, C. Choi, B. Bihari, and T. Chen, "Optoelectronic integration of polymer waveguide array and metal-semiconductor-metal photodetector through micromirror couplers," IEEE Photon. Technol. Lett. 13, 355-357 (2001).
19. M. Kagami, A. Kawasaki, and H. Ito, "A polymer optical waveguide with out-of-plane branching mirrors for surface-normal optical interconnections," J. Lightwave Technol. 19, 1949-1955 (2001).
20. J. R. Jump, YACSIM Reference Manual (Rice University, 1993), http://wwwece.rice.edu/rppt.html.
21. F. Petrini, E. Frachtenberg, and A. Hoisie, "Performance evaluation of the quadries interconnection network," Cluster Comput. 6, 125-142 (2003).
22. S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, "The Alpha 21364 network architecture," IEEE Micro 22, 26-35 (2002).
23. M. Galles, "Spider: a high-speed network interconnect," IEEE Micro 17, 34-39 (1997).
24. Mellanox Technologies, http://www.mellanox.com/.
25. W. J. Dally and B. Towles, Principles and P. of Interconnection Networks (Morgan Kaufmann, 2004).