Partial bus-invert coding for power optimization of application-specific systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 2, 2001, Pages 377-383

  Shin, Youngsoo ^a   Chae, Soo Ik ^b   Choi, Kiyoung ^b  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b Seoul National University   (South Korea)

Author keywords

Digital complementary metal oxide semiconductor (CMOS); Low power dissipation; Memory; Switching activity; System level; Tradeoffs

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENCODING (SYMBOLS); HEURISTIC METHODS; OPTIMIZATION;

DIGITAL COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR; HEURISTIC ALGORITHM; MULTIWAY PARTIAL BUS-INVERT CODING; PARTIAL BUS-INVERT CODING; POWER OPTIMIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0035301452     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.924059     Document Type: Article

References (13)

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