Coupling-aware high-level interconnect synthesis for low power

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 609-613

  Lyuh, Chun Gi ^a   Kim, Taewhan ^a   Kim, Ki Wook ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Pluris Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATAFLOW GRAPH; HIGH LEVEL INTERCONNECT SYNTHESIS; INTERCONNECT POWER MODEL; SYSTEM ON-CHIP; ULTRA DEEP SUBMICRON TECHNOLOGY;

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTERCONNECTION NETWORKS; OPTIMIZATION; ULSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036907052     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774662     Document Type: Conference Paper

References (19)

1. Y. Shin and T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Systems," Proc. of DAC, 2001.
2. P. R. Panda and N. D. Dutt, "Low-Power Memory Mapping Through Reducing Address Bus Activity," IEEE Tran. on VLSI Systems, Vol. 7, No. 3, 1999.
3. S. Ramprasad, N. R. Shanbhag, and I. Hajj, "A Coding Framework for Low-Power Address and Data Busses," IEEE Trans. on VLSI Systems, Vol. 3, No. 1, 1995.
4. H. Mehta, R. M. Owens and M. J. Irwin, "Some issues in Gray code addressing," Proc. of Sixth Great Lakes Symposium on VLSI, 1996.
5. C. L. Su, C. Y. Tsui, and A. M. Despain, "Saving power in the control path of embedded processors," IEEE Design and Test of Computers, Vol. 11, No. 4, 1994.
6. E. Musoll, T. Lang and J. Cortadella, "Working-zone encoding for reducing the energy in microprocessor address buses," IEEE Trans. on VLSI Systems, Vol. 6, No. 4, 1998.
7. M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. on VLSI Systems, Vol. 3, No. 1, 1995.
8. S. Hong, T. Kim, U. Narayanan and K.-S. Chung, "Decomposition of bus-invert coding for low-power I/O," Journal of Circuits, Systems and Computers, Vol. 10, Nos. 1 & 2, 2000.
9. K.-W. Kim, K.-H. Baek, N. Shanbhag, C. L. Liu, and S.-M. Kang, "Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design," Proc. of ICCAD, 2000.
10. A. Dasgupta and R. Karri, "Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis," Proc. of ISLPED, 1995.
11. A. Dasgupta and R. Karri, "High-Reliability, Low-Energy Microarchitecture Synthesis," IEEE Trans. on CAD, Vol. 17, No. 12, 1998.
12. J.-M. Chang and M. Pedram, "Register Allocation and binding for Low Power," Proc. of DAC, 1995.
13. J.-M. Chang and M. Pedram, "Module Assignment for Low Power," Proc. of EDAC, 1996.
14. S. Hong and T. Kim, "Bus Optimization for Low-Power Data Path Synthesis based on Network Flow Method," Proc. of ICCAD, 2000.
15. C. Lyuh, T. Kim and C. L. Liu, "An Integrated Data Path Optimization for Low Power Based on Network Flow Method," Proc. of ICCAD, 2001.
16. C H. Papadimitriou and K. Steiglitz, Combinatorial Optimization, Prentice Hall, pp. 247-254, 1982.
17. A. Aho, J. Hopcroft, and J. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley, 1974.
18. P. R. Panda and N. D. Dutt, "High-Level Synthesis Design Repository", Proc. of ISSS (http://www.ics.uci.edu/dutt), 1995.
19. L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, "Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems," Proc. of Seventh Great Lakes Symposium on VLSI, 1997.