Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Design Automation for Embedded Systems

Volumn 10, Issue 2-3, 2005, Pages 105-125

  Dhanwada, Nagu ^a   Bergamaschi, Reinaldo A ^b   Dungan, William W ^a   Nair, Indira ^b   Gramann, Paul ^c   Dougherty, William E ^a   Lin, Ing Chao ^d  

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM   (United States)

^d PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Architecture modeling; CoreConnect; Power analysis; PowerPC; SystemC; Transaction level modeling

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PARAMETER ESTIMATION; POWER CONTROL;

ARCHITECTURE MODELING; CORECONNECT; POWER ANALYSIS; POWERPC; SYSTEMC; TRANSACTION LEVEL MODELING;

PERSONAL COMPUTERS;

EID: 33748987343     PISSN: 09295585     EISSN: 15728080     Source Type: Journal    
DOI: 10.1007/s10617-006-9586-7     Document Type: Article

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