Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 163-169

  Givargis, T D ^a   Vahid, F ^a   Henkel, J ^b  

^a University of California ^*  (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Circuit simulation; Codecs; Computational modeling; Computer science; Energy consumption; Hardware design languages; Intellectual property; Microprocessors; Power engineering and energy; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; C++ (PROGRAMMING LANGUAGE); CIRCUIT SIMULATION; COMPUTER HARDWARE; COMPUTER SCIENCE; COMPUTER SIMULATION LANGUAGES; COMPUTER SOFTWARE; ENERGY UTILIZATION; INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; MODELING LANGUAGES; SYNTHESIS (CHEMICAL); SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

CODECS; COMPUTATIONAL MODEL; HARDWARE DESIGN LANGUAGE; POWER ENGINEERING AND ENERGIES; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT DESIGN;

EID: 84949994098     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874044     Document Type: Conference Paper

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