Function-level power estimation methodology for microprocessors

Proceedings-Design Automation Conference

Volumn , Issue , 2000, Pages 810-813

  Qu, Gang ^a   Kawabe, Naoyuki ^b   Usami, Kimiyoshi ^b   Potkonjak, Miodrag ^a  

^a University of California   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; BUFFER STORAGE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ERRORS; MICROCOMPUTERS; VLSI CIRCUITS;

FUNCTION LEVEL POWER ESTIMATION METHODOLOGY; POWER DATA BANK; POWER SIMULATOR;

COMPUTER SOFTWARE;

EID: 0033685331     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855425     Document Type: Article

References (15)

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