Hardware implementation of an inverse function delayed neural network using stochastic logic

IEICE Transactions on Information and Systems

Volumn E89-D, Issue 9, 2006, Pages 2572-2578

  Li, Hongge ^a   Hayakawa, Yoshihiro ^a   Sato, Shigeo ^a   Nakajima, Koji ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Associative memory; Field programmable gate array (FPGA); Inverse function delayed model; Stochastic logic

Indexed keywords

ASSOCIATIVE STORAGE; FIELD PROGRAMMABLE GATE ARRAYS; INVERSE PROBLEMS; LOGIC CIRCUITS; MATHEMATICAL MODELS; RANDOM PROCESSES;

ASSOCIATIVE MEMORY; INVERSE FUNCTION DELAYED MODEL; STOCHASTIC LOGIC;

NEURAL NETWORKS;

EID: 33748762219     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e89-d.9.2572     Document Type: Article

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