-
1
-
-
0021835689
-
'Neural' computation of decisions optimization problems
-
J.J Hopfield and D.W. Tank, "'Neural' computation of decisions optimization problems," Biological Cybern., vol.52, pp.141-152, 1985.
-
(1985)
Biological Cybern.
, vol.52
, pp. 141-152
-
-
Hopfield, J.J.1
Tank, D.W.2
-
2
-
-
0024684015
-
Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm
-
June
-
Michel Verleysen, B. Sirletti, A. M. Vandemeulebroecke and P. A. Jespers, "Neural networks for High-Storage Content-Addressable Memory: VLSI circuit and learning Algorithm" IEEE Journal of solid-state circuits, vol.24, No.3, June 1989.
-
(1989)
IEEE Journal of Solid-state Circuits
, vol.24
, Issue.3
-
-
Verleysen, M.1
Sirletti, B.2
Vandemeulebroecke, A.M.3
Jespers, P.A.4
-
3
-
-
0023361987
-
Asynchronous VLSI neural networks using pulse-stream arithmetic
-
June
-
Alan F. Murray and A.V. W. Smith, "Asynchronous VLSI Neural Networks Using Pulse-Stream Arithmetic," IEEE Journal of Solid-State circuits, vol.23, No.3, June 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, Issue.3
-
-
Murray, A.F.1
Smith, A.V.W.2
-
4
-
-
0036522786
-
Hardware implementation of a DBM network with nonmonotonic neurons
-
M. Kinjo, S. Sato, K. Nakajima, "Hardware implementation of a DBM network with nonmonotonic neurons," IEICE Trans.Inform.Syst., vol. E85-D, pp.558-567, 2002.
-
(2002)
IEICE Trans.Inform.Syst.
, vol.E85-D
, pp. 558-567
-
-
Kinjo, M.1
Sato, S.2
Nakajima, K.3
-
5
-
-
0025532312
-
A VLSI architecture for high-performance, low-cost, on-chip learning
-
D. Hammerstrom, "A VLSI architecture for high-performance, low-cost, on-chip learning," proc, IEEE/INNS Inter, Joint conf. Neaural Networs, vol.2, 1990.
-
(1990)
Proc, IEEE/INNS Inter, Joint Conf. Neaural Networs
, vol.2
-
-
Hammerstrom, D.1
-
6
-
-
34250853947
-
A digital architecture employing stochasticism for the simulation of hopfield neural network
-
May
-
David E. van den bout, T. Miller, "A Digital Architecture Employing Stochasticism for the Simulation of Hopfield Neural network", IEEE Trans. On circuits and systems, vol.36, No.5, May 1989.
-
(1989)
IEEE Trans. on Circuits and Systems
, vol.36
, Issue.5
-
-
Van Den Bout, D.E.1
Miller, T.2
-
7
-
-
0026866931
-
Functional abilities of a stochastic logic neural network
-
May
-
Y. Kondo, Y. Sawada, "Functional Abilities of a Stochastic Logic Neural Network" IEEE Trans. On neural network, vol. 3, No. 3, May 1992.
-
(1992)
IEEE Trans. on Neural Network
, vol.3
, Issue.3
-
-
Kondo, Y.1
Sawada, Y.2
-
8
-
-
0029206490
-
Random noise effects in pulse-mode digital multiplayer neural networks
-
January
-
Y. C. Kim, M. A. Shanblatt, "Random Noise Effects in Pulse-Mode Digital Multiplayer Neural Networks" IEEE Trans. On neural network, vol. 6, No. 1, January 1995.
-
(1995)
IEEE Trans. on Neural Network
, vol.6
, Issue.1
-
-
Kim, Y.C.1
Shanblatt, M.A.2
-
9
-
-
0032683138
-
Frequency-based multiplayer neural network with on-chip learning and enhanced neuron characteristics
-
May
-
H. Hikawa, "Frequency-Based Multiplayer Neural Network with On-chip Learning and Enhanced Neuron Characteristics" IEEE Trans. On neural network, vol. 10, No. 3, May 1999.
-
(1999)
IEEE Trans. on Neural Network
, vol.10
, Issue.3
-
-
Hikawa, H.1
-
10
-
-
0015435130
-
Learning patterns and pattern sequences by self-organizing nets of threshold elements
-
S.I. Amari, "Learning patterns and pattern sequences by self-organizing nets of threshold elements", IEEE Trans.Comput. 21 1197-206, 1972.
-
(1972)
IEEE Trans.Comput.
, vol.21
, pp. 1197-1206
-
-
Amari, S.I.1
-
11
-
-
26044436143
-
Characteristics of inverse delayed model for neural computation
-
K. Nakajima, Y. Hayakawa. "Characteristics of Inverse Delayed Model for Neural Computation", NOLTA 10, 2002.
-
(2002)
NOLTA
, vol.10
-
-
Nakajima, K.1
Hayakawa, Y.2
-
12
-
-
0242695738
-
Implementation of a new neuronchip using stochastic logic
-
September
-
S. Sato, K. Nemoto, S. Skimoto, M.Kinjo, K. Nakajima, "Implementation of a New Neuronchip Using Stochastic Logic" IEEE Trans. On neural network, vol. 14, No.5, September 2003.
-
(2003)
IEEE Trans. on Neural Network
, vol.14
, Issue.5
-
-
Sato, S.1
Nemoto, K.2
Skimoto, S.3
Kinjo, M.4
Nakajima, K.5
-
13
-
-
0036603635
-
An architecture of small-scaled neuro-hardware using probabilistically coded pulse Neurons
-
T. Kawashima, A.Ishiguro, A.Okuma, "An architecture of small-scaled neuro-hardware using probabilistically coded pulse Neurons", Electrical Engineering in Japan,Vol.139, No.4,2002.
-
(2002)
Electrical Engineering in Japan
, vol.139
, Issue.4
-
-
Kawashima, T.1
Ishiguro, A.2
Okuma, A.3
|