Implementation of a New Neurochip Using Stochastic Logic

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1122-1127

  Sato, Shigeo ^a   Nemoto, Ken ^a   Akimoto, Shunsuke ^a   Kinjo, Mitsunaga ^a   Nakajima, Koji ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Boltzmann machine (BM); Large scale integration (LSI) implementation; Nonmonotonic neuron; Simulated annealing; Stochastic logic; Traveling salesman problem

Indexed keywords

DIGITAL CIRCUITS; LEARNING SYSTEMS; LOGIC DESIGN; LOGIC GATES; LSI CIRCUITS; SIMULATED ANNEALING; STOCHASTIC PROGRAMMING; TRAVELING SALESMAN PROBLEM;

NONMONOTONIC NEURONS; STOCHASTIC LOGIC;

NEURAL NETWORKS;

EID: 0242695738     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816341     Document Type: Article

References (24)

1. J. E. Dayhoff, Neural Network Architectures: An Introduction. New York: Wiley, 1990.
2. M. Morita, "Associative memory with nonmonotone dynamics," Neural Networks, vol. 6, pp. 115-126, 1993.
3. S. Yoshizawa, M. Morita, and S. Amari, "Capacity of associative memory using a nonmonotonic neuron model," Neural Networks, vol. 6. pp. 167-176, 1993.
4. T. Fukai, J. Kim, and M. Shiino, "Retrieval properties of analog neural networks and the nonmonotonicity of transfer functions," Neural Networks, vol. 8, pp. 391-404, 1995.
5. H.-F. Yanai and S. Amari, "Auto-associative memory with two-stage dynamics of nonmonotonic neurons," IEEE Trans. Neural Networks, vol. 7. pp. 803-815, July 1996.
6. M. Okada, "Notions of associative memory and sparse coding," Neural Networks, vol. 9, pp. 1429-1458, 1996.
7. M. Morita, "Memory and learning of sequential patterns by nonmonotone neural networks," Neural Networks, vol. 9, pp. 1477-1489, 1996.
8. _, "Computational study on the neural mechanism of sequential pattern memory," Cogn. Brain Res., vol. 5, pp. 137-146, 1996.
9. M. Kinjo, S. Sato, and K. Nakajima, "Hardware implementation of a DBM network with nonmonotonic neurons," IEICE Trans. Inform. Syst., vol. E85-D, pp. 558-567, 2002.
10. D. E. van den Bout and T. K. Miller III, "A digital architecture employing stochasticism for the simulation of Hopfield neural network," IEEE Trans. Circuits Syst., vol. 36, pp. 732-738, May 1989.
11. A. F. Murray, D. D. Korso, and L. Tarassenko, "Pulse-stream VLSI neural networks mixing analog and digital techniques." IEEE Trans. Neural Networks, vol. 2, pp. 193-204, June 1991.
12. G. Moon, M. E. Zaghloul, and R. E. Newcomb, "VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells," IEEE Trans. Neural Networks, vol. 3, pp. 394-403, Mar. 1992.
13. Y. Kondo and Y. Sawada, "Functional abilities of a stochastic logic neural network." IEEE Trans. Neural Networks, vol. 3, pp. 434-443, May 1993.
14. S. Sato, M. Yumine, T. Yama, J. Murota, K. Nakajima, and Y. Sawada, "LSI neural chip of pulse-output network with programmable synapse," IEICE Trans. Electron., vol. E78-C, pp. 94-100, 1995.
15. Y. Hirai and M. Yasunaga, "A PDM digital neural network system with 1 000 neurons fully interconnected via 1 000 000 6-bit synapses." in Proc. 1996 Int. Conf. Neural Information Processing, 1996, pp. 1251-1256.
16. T. Morie, J. Funakoshi, M. Nagata, and A. Iwata, "An analog-digital merged neural circuit using pulse width modulation technique," IEICE Trans. Fund. Electron. Commun. Comput. Sci., vol. E82-A, pp. 356-363, 1999.
17. B. D. Brown and H. C. Card, "Stochastic neural computation I: Computational elements," IEEE Trans. Comput., vol. 50, pp. 891-905, Sept. 2001.
18. B. R. Gains. Advances in Information Systems Science. New York, NY: Plenum, 1969. Stochastic Computing Systems.
19. G. E. Hinton and T. J. Sejnowski. Parallel Distributed Processing. Cambridge, MA: MIT Press, 1986. Learning and Releaming in Boltzmann Machines.
20. J. J. Hopfield and D. W. Tank, "Neural computation of decisions in optimization problems," Biol. Cybern., vol. 52, pp. 141-152, 1985.
21. S. Geman and D. Geman, "Stochastic relaxation, Gibbs distribution, and the Baysian restoration of images," IEEE Trans. Pattern Anal. Machine Intell., vol. PAMI-6, pp. 721-741, Nov. 1984.
22. K. Nemoto, M. Kinjo, S. Sato, and K. Nakajima, "A nonmonotonic neurochip using stochastic logic," in Proc. 2001 Int. Symp. Nonlinear Theory Applications, 2001, pp. 605-608.
23. K. Aihara, O. Fujita, and K. Uchimura. "A sparse memory access architecture for digital neural network LSIs," IEICE Trans. Electron., vol. E80-C, pp. 996-1002, 1997.
24. S. Komori Y. Arima, Y. Kondo, H. Tsubota, K. Tanaka, and K. Kyuma, "A 3.2 GFLOPS neural network accelerator," IEICE Trans. Electron., vol. E80-C, pp. 859-867, 1997.