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Volumn E85-A, Issue 9, 2002, Pages 2149-2158

A self-learning analog neural processor

Author keywords

Analog VLSI; Gradient descent learning; Multi layer perceptron; Neural networks; On chip learning

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEARNING ALGORITHMS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

EID: 0036740528     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (3)

References (18)
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  • 4
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    • G.M. Bo, D.D. Caviglia, H. Chiblé, and M. Valle, "A circuit architecture for analog on-chip back propagation learning with local learning rate adaptation," Analog Integrated Circuits and Signal Processing, vol.18, nos.2-3, pp.163-173, 1999.
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    • Bo, G.M.1    Caviglia, D.D.2    Chiblé, H.3    Valle, M.4
  • 5
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    • Analog VLSI implementation of an on-chip learning neural network
    • ed. G. Cauwenberghs and M. Bayoumi, Kluwer Academic
    • G.M. Bo, D.D. Caviglia, H. Chiblé, and M. Valle. "Analog VLSI implementation of an on-chip learning neural network," in Learning on Silicon - Adaptive VLSI Neural Systems, ed. G. Cauwenberghs and M. Bayoumi, pp.305-332, Kluwer Academic, 1999.
    • (1999) Learning on Silicon - Adaptive VLSI Neural Systems , pp. 305-332
    • Bo, G.M.1    Caviglia, D.D.2    Chiblé, H.3    Valle, M.4
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.