메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 677-682

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTATIONAL GEOMETRY; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RINGS (COMPONENTS);

EID: 33748614838     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118459     Document Type: Conference Paper
Times cited : (6)

References (13)
  • 1
    • 0032026503 scopus 로고    scopus 로고
    • Computer-aided design considerations for mixed-signal coupling in RF integrated circuits
    • Mar.
    • N. Verghese and D. Allstot, "Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits," IEEE J. Solid-State Circuits, pp. 314-323, Mar. 1998.
    • (1998) IEEE J. Solid-state Circuits , pp. 314-323
    • Verghese, N.1    Allstot, D.2
  • 2
    • 0027576336 scopus 로고
    • Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
    • Apr.
    • D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, Vol. 28, pp. 420-430, Apr. 1993.
    • (1993) IEEE J. Solid-state Circuits , vol.28 , pp. 420-430
    • Su, D.K.1    Loinaz, M.J.2    Masui, S.3    Wooley, B.A.4
  • 3
    • 0033703261 scopus 로고    scopus 로고
    • A S-calable substrate noise coupling model for design of mixed-signal IC's
    • June
    • A. Samavedam, A. Sadate, K. Mayaram, T. S. Fiez, "A S-calable Substrate Noise Coupling Model for Design of Mixed-Signal IC's," IEEE J. Solid-State Circuits, pp. 895-904, June 2000.
    • (2000) IEEE J. Solid-state Circuits , pp. 895-904
    • Samavedam, A.1    Sadate, A.2    Mayaram, K.3    Fiez, T.S.4
  • 6
    • 84962227737 scopus 로고    scopus 로고
    • Substrate noise analysis with compact digital noise injection and substrate models
    • Jan
    • M. Nagata, Y. Murasaka, Y. Nishimori, T. Morie, and A. I-wata "Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models" in Proc. ASP-DAC, pp. 71-76, Jan 2002.
    • (2002) Proc. ASP-DAC , pp. 71-76
    • Nagata, M.1    Murasaka, Y.2    Nishimori, Y.3    Morie, T.4    I-Wata, A.5
  • 8
    • 0035274508 scopus 로고    scopus 로고
    • Physical design guides for substrate noise reduction in C-MOS digital circuits
    • Mar.
    • M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical Design Guides for Substrate Noise Reduction in C-MOS Digital Circuits," IEEE J. Solid-State Circuits, pp. 539-549, Mar. 2001.
    • (2001) IEEE J. Solid-state Circuits , pp. 539-549
    • Nagata, M.1    Nagai, J.2    Hijikata, K.3    Morie, T.4    Iwata, A.5
  • 10
    • 5444253380 scopus 로고    scopus 로고
    • An experimental study on substrate coupling in bipolar/BiCMOS technologies
    • Oct.
    • M. Pfost, P. Brenner, T. Huttner, A. Romanyuk, "An Experimental Study on Substrate Coupling in Bipolar/BiCMOS Technologies," IEEE J. Solid-State Circuits, pp. 1755-1763, Oct. 2004.
    • (2004) IEEE J. Solid-state Circuits , pp. 1755-1763
    • Pfost, M.1    Brenner, P.2    Huttner, T.3    Romanyuk, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.