Chip-level substrate noise analysis with network reduction by fundamental matrix computation

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 482-487

  Murasaka, Yoshitaka ^a   Nagata, Makoto ^a   Ohmoto, Takafumi ^a   Morie, Takashi ^a   Iwata, Atsushi ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MATRIX ALGEBRA;

EQUIVALENT CIRCUIT MODEL; FUNDAMENTAL MATRIX; NETWORK REDUCTION; REDUCTION TECHNIQUES; SIMULATION ERROR; SUBSTRATE NOISE; SUBSTRATE NOISE ANALYSIS; SUBSTRATE NOISE SIMULATION;

SUBSTRATES;

EID: 33748619403     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2001.915275     Document Type: Article

References (9)

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