Substrate noise analysis with compact digital noise injection and substrate models

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 71-76

  Nagata, M ^a   Murasaka, Y ^b   Nishimori, Y ^a   Morie, T ^a   Iwata, A ^a,b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b A R Tec Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; DESIGN; MATRIX ALGEBRA; TIME SERIES ANALYSIS;

CONVENTIONAL DESIGN; DIGITAL NOISE; PARASITIC CAPACITANCE; SUBSTRATE MODEL; SUBSTRATE NOISE; SUBSTRATE NOISE ANALYSIS; SYSTEM LEVEL SIMULATION; TIME DOMAIN POWER;

TIME DOMAIN ANALYSIS;

EID: 84962227737     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994888     Document Type: Conference Paper

References (8)

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7. M. Nagata, J. Nagai, T. Morie, and A. Iwata, "Measurements and analyses of substrate noise waveform in mixed signal IC environment," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 19(6):671-678, June 2000.
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